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f220e7cb76
We want to run the Machine Scheduler instead of the List Scheduler after RA. Checked with a performance run on a Power 9 machine with SPEC 2006 and while some benchmarks improved and others degraded the geomean was slightly improved with the Machine Scheduler. Differential Revision: https://reviews.llvm.org/D45265 llvm-svn: 336295
126 lines
3.6 KiB
LLVM
126 lines
3.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
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; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
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; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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@glob = common local_unnamed_addr global i64 0, align 8
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define i64 @test_llnesll(i64 %a, i64 %b) {
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; CHECK-LABEL: test_llnesll:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xor r3, r3, r4
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; CHECK-NEXT: addic r4, r3, -1
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; CHECK-NEXT: subfe r3, r4, r3
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ne i64 %a, %b
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%conv1 = zext i1 %cmp to i64
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ret i64 %conv1
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}
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define i64 @test_llnesll_sext(i64 %a, i64 %b) {
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; CHECK-LABEL: test_llnesll_sext:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xor r3, r3, r4
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; CHECK-NEXT: subfic r3, r3, 0
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; CHECK-NEXT: subfe r3, r3, r3
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ne i64 %a, %b
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%conv1 = sext i1 %cmp to i64
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ret i64 %conv1
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}
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define i64 @test_llnesll_z(i64 %a) {
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; CHECK-LABEL: test_llnesll_z:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addic r4, r3, -1
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; CHECK-NEXT: subfe r3, r4, r3
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ne i64 %a, 0
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%conv1 = zext i1 %cmp to i64
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ret i64 %conv1
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}
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define i64 @test_llnesll_sext_z(i64 %a) {
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; CHECK-LABEL: test_llnesll_sext_z:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: subfic r3, r3, 0
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; CHECK-NEXT: subfe r3, r3, r3
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ne i64 %a, 0
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%conv1 = sext i1 %cmp to i64
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ret i64 %conv1
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}
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define void @test_llnesll_store(i64 %a, i64 %b) {
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; CHECK-LABEL: test_llnesll_store:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
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; CHECK-NEXT: xor r3, r3, r4
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; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
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; CHECK-NEXT: addic r5, r3, -1
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; CHECK-NEXT: subfe r3, r5, r3
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; CHECK-NEXT: std r3, 0(r4)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ne i64 %a, %b
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%conv1 = zext i1 %cmp to i64
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store i64 %conv1, i64* @glob, align 8
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ret void
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}
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define void @test_llnesll_sext_store(i64 %a, i64 %b) {
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; CHECK-LABEL: test_llnesll_sext_store:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
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; CHECK-NEXT: xor r3, r3, r4
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; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
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; CHECK-NEXT: subfic r3, r3, 0
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; CHECK-NEXT: subfe r3, r3, r3
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; CHECK-NEXT: std r3, 0(r4)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ne i64 %a, %b
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%conv1 = sext i1 %cmp to i64
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store i64 %conv1, i64* @glob, align 8
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ret void
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}
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define void @test_llnesll_z_store(i64 %a) {
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; CHECK-LABEL: test_llnesll_z_store:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
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; CHECK-NEXT: addic r5, r3, -1
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; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
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; CHECK-NEXT: subfe r3, r5, r3
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; CHECK-NEXT: std r3, 0(r4)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ne i64 %a, 0
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%conv1 = zext i1 %cmp to i64
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store i64 %conv1, i64* @glob, align 8
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ret void
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}
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define void @test_llnesll_sext_z_store(i64 %a) {
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; CHECK-LABEL: test_llnesll_sext_z_store:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
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; CHECK-NEXT: subfic r3, r3, 0
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; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
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; CHECK-NEXT: subfe r3, r3, r3
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; CHECK-NEXT: std r3, 0(r4)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ne i64 %a, 0
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%conv1 = sext i1 %cmp to i64
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store i64 %conv1, i64* @glob, align 8
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ret void
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}
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