Patrick Holland 0114258120 [MCA] [In-order pipeline] Fix for 0 latency instruction causing assertion to fail. ... 0 latency instructions now get processed and retired properly within the in-order pipeline. Had to fix a bug within TimelineView.cpp as well that would show up when a 0 latency instruction was the first instruction in the source. Differential Revision: https://reviews.llvm.org/D104675		2021-06-22 10:18:39 -07:00
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HardwareUnits	[MCA] [RegisterFile] Allow for skipping Defs with RegID of 0 (rather than assert(RegID) like we do before this patch).	2021-06-17 11:52:43 -07:00
Stages	[MCA] [In-order pipeline] Fix for 0 latency instruction causing assertion to fail.	2021-06-22 10:18:39 -07:00
CMakeLists.txt	Reapply "[MCA] Adding the CustomBehaviour class to llvm-mca".	2021-06-16 16:54:48 +01:00
CodeEmitter.cpp	[MCA][NFCI] Minor changes to InstrBuilder and Instruction.	2021-05-31 17:05:13 +01:00
Context.cpp	Reapply "[MCA] Adding the CustomBehaviour class to llvm-mca".	2021-06-16 16:54:48 +01:00
CustomBehaviour.cpp	[MCA] Anchoring the vtable of CustomBehaviour	2021-06-16 12:43:58 -07:00
HWEventListener.cpp
InstrBuilder.cpp	Reapply "[MCA] Adding the CustomBehaviour class to llvm-mca".	2021-06-16 16:54:48 +01:00
Instruction.cpp	[MCA] Improved handling of negative read-advance cycles.	2021-03-23 14:47:23 +00:00
Pipeline.cpp
Support.cpp