Sander de Smalen bb0cf5cecf [AArch64] Disallow vector operand if FPR128 Q register is required. ... Patch https://reviews.llvm.org/D41445 changed the behaviour of 'isReg()' to also return 'true' if the parsed register operand is a vector register. Code in the AsmMatcher checks if a register is a subclass of the expected register class. However, even though both parsed registers map to the same physical register, the 'v' register is of kind 'NeonVector', where 'q' is of type Scalar, where isSubclass() does not distinguish between the two cases. The solution is to use an AsmOperand instead of the register directly, and use the PredicateMethod to distinguish the two operands. This fixes for example: ldr v0, [x0] // 'v0' is an invalid operand for this instruction ldr q0, [x0] // valid Reviewers: aemerson, Gerolf, SjoerdMeijer, javed.absar Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D46310 llvm-svn: 331755		2018-05-08 10:01:04 +00:00
..
AsmParser	[AArch64][SVE] Asm: Support for LD1RQ load-and-replicate quad-word vector instructions.	2018-05-02 08:49:08 +00:00
Disassembler	[AArch64][SVE] Asm: Support for contiguous LD1 (scalar+scalar) load instructions.	2018-04-20 12:52:01 +00:00
InstPrinter	[AArch64][SVE] Asm: Add AsmOperand classes for SVE gather/scatter addressing modes.	2018-04-25 09:26:47 +00:00
MCTargetDesc	[COFF, ARM64] Hook up a few remaining relocations	2018-05-02 18:24:37 +00:00
TargetInfo
Utils	[AArch64][SVE] Asm: Predicate patterns	2018-01-22 10:46:00 +00:00
AArch64.h
AArch64.td	[PATCH] [AArch64] Add new target feature to fuse conditional select	2018-02-23 19:27:43 +00:00
AArch64A53Fix835769.cpp
AArch64A57FPLoadBalancing.cpp	[AArch64] Change std::sort to llvm::sort in response to r327219	2018-04-04 18:20:28 +00:00
AArch64AdvSIMDScalarPass.cpp
AArch64AsmPrinter.cpp	Remove \brief commands from doxygen comments.	2018-05-01 15:54:18 +00:00
AArch64CallingConvention.h
AArch64CallingConvention.td	AArch64: Implement support for the shadowcallstack attribute.	2018-04-04 21:55:44 +00:00
AArch64CallLowering.cpp	[IR][CodeGen] Remove dependency on EVT from IR/Function.cpp. Move EVT to CodeGen layer.	2018-03-29 17:21:10 +00:00
AArch64CallLowering.h
AArch64CleanupLocalDynamicTLSPass.cpp
AArch64CollectLOH.cpp	Revert "[CodeGen] Move printing '\n' from MachineInstr::print to MachineBasicBlock::print"	2018-02-19 15:08:49 +00:00
AArch64CondBrTuning.cpp
AArch64ConditionalCompares.cpp
AArch64ConditionOptimizer.cpp
AArch64DeadRegisterDefinitionsPass.cpp
AArch64ExpandPseudoInsts.cpp	Remove \brief commands from doxygen comments.	2018-05-01 15:54:18 +00:00
AArch64FalkorHWPFFix.cpp	[AArch64][Falkor] Fix bug in Falkor HWPF collision avoidance pass.	2018-04-10 21:43:03 +00:00
AArch64FastISel.cpp	Remove \brief commands from doxygen comments.	2018-05-01 15:54:18 +00:00
AArch64FrameLowering.cpp	[AArch64] Place the first ldp at the end when ReverseCSRRestoreSeq is true	2018-04-27 15:30:54 +00:00
AArch64FrameLowering.h	Remove \brief commands from doxygen comments.	2018-05-01 15:54:18 +00:00
AArch64GenRegisterBankInfo.def
AArch64InstrAtomics.td	[AArch64] Improve v8.1-A code-gen for atomic load-and	2018-02-12 17:03:11 +00:00
AArch64InstrFormats.td	[AArch64] Disallow vector operand if FPR128 Q register is required.	2018-05-08 10:01:04 +00:00
AArch64InstrInfo.cpp	Remove \brief commands from doxygen comments.	2018-05-01 15:54:18 +00:00
AArch64InstrInfo.h	Remove \brief commands from doxygen comments.	2018-05-01 15:54:18 +00:00
AArch64InstrInfo.td	[AArch64] Disallow vector operand if FPR128 Q register is required.	2018-05-08 10:01:04 +00:00
AArch64InstructionSelector.cpp	[globalisel] Update GlobalISel emitter to match new representation of extending loads	2018-05-05 20:53:24 +00:00
AArch64ISelDAGToDAG.cpp	Remove \brief commands from doxygen comments.	2018-05-01 15:54:18 +00:00
AArch64ISelLowering.cpp	Fix a bunch of places where operator-> was used directly on the return from dyn_cast.	2018-05-05 01:57:00 +00:00
AArch64ISelLowering.h	Remove \brief commands from doxygen comments.	2018-05-01 15:54:18 +00:00
AArch64LegalizerInfo.cpp	[globalisel] Update GlobalISel emitter to match new representation of extending loads	2018-05-05 20:53:24 +00:00
AArch64LegalizerInfo.h
AArch64LoadStoreOptimizer.cpp	[CodeGen] Use RegUnits to track register aliases (NFC)	2018-04-27 18:44:37 +00:00
AArch64MachineFunctionInfo.h	Remove \brief commands from doxygen comments.	2018-05-01 15:54:18 +00:00
AArch64MacroFusion.cpp	Remove \brief commands from doxygen comments.	2018-05-01 15:54:18 +00:00
AArch64MacroFusion.h
AArch64MCInstLower.cpp	Move TargetLoweringObjectFile from CodeGen to Target to fix layering	2018-03-23 23:58:19 +00:00
AArch64MCInstLower.h
AArch64PBQPRegAlloc.cpp
AArch64PBQPRegAlloc.h
AArch64PerfectShuffle.h
AArch64PromoteConstant.cpp
AArch64RedundantCopyElimination.cpp
AArch64RegisterBankInfo.cpp
AArch64RegisterBankInfo.h
AArch64RegisterBanks.td
AArch64RegisterInfo.cpp	AArch64: Implement support for the shadowcallstack attribute.	2018-04-04 21:55:44 +00:00
AArch64RegisterInfo.h	[AArch64] Implement dynamic stack probing for windows	2018-02-17 14:26:32 +00:00
AArch64RegisterInfo.td	[AArch64] Disallow vector operand if FPR128 Q register is required.	2018-05-08 10:01:04 +00:00
AArch64SchedA53.td	[AArch64] Clean-up a few over-eager regexps in models.	2018-03-23 11:00:42 +00:00
AArch64SchedA57.td
AArch64SchedA57WriteRes.td
AArch64SchedCyclone.td
AArch64SchedExynosM1.td	[AArch64][NFC] Make all ProcResource definitions include their SchedModel.	2018-02-01 12:12:01 +00:00
AArch64SchedExynosM3.td	[AArch64] Adjust the cost model for Exynos M3	2018-04-03 22:57:17 +00:00
AArch64SchedFalkor.td	[TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU.	2018-03-18 19:56:15 +00:00
AArch64SchedFalkorDetails.td	[AArch64][Falkor] Correct load/store increment scheduling details	2018-03-20 13:46:35 +00:00
AArch64SchedKryo.td	[TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU.	2018-03-18 19:56:15 +00:00
AArch64SchedKryoDetails.td
AArch64SchedThunderX2T99.td	[AArch64] Clean-up a few over-eager regexps in models.	2018-03-23 11:00:42 +00:00
AArch64SchedThunderX.td	[TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU.	2018-03-18 19:56:15 +00:00
AArch64Schedule.td
AArch64SelectionDAGInfo.cpp
AArch64SelectionDAGInfo.h
AArch64SIMDInstrOpt.cpp	[TargetSchedule] shrink interface for init(); NFCI	2018-04-08 19:56:04 +00:00
AArch64StorePairSuppress.cpp	[TargetSchedule] shrink interface for init(); NFCI	2018-04-08 19:56:04 +00:00
AArch64Subtarget.cpp	AArch64: Implement support for the shadowcallstack attribute.	2018-04-04 21:55:44 +00:00
AArch64Subtarget.h	Remove \brief commands from doxygen comments.	2018-05-01 15:54:18 +00:00
AArch64SVEInstrInfo.td	[AArch64][SVE] Asm: Support for LDR/STR fill and spill instructions.	2018-05-02 13:32:39 +00:00
AArch64SystemOperands.td	[AArch64] Fix spelling of ICH_ELRSR_EL2 system register	2018-02-06 09:39:04 +00:00
AArch64TargetMachine.cpp	MachO: trap unreachable instructions	2018-04-13 22:25:20 +00:00
AArch64TargetMachine.h
AArch64TargetObjectFile.cpp
AArch64TargetObjectFile.h	Move TargetLoweringObjectFile from CodeGen to Target to fix layering	2018-03-23 23:58:19 +00:00
AArch64TargetTransformInfo.cpp	Remove \brief commands from doxygen comments.	2018-05-01 15:54:18 +00:00
AArch64TargetTransformInfo.h	[TTI, AArch64] Add transpose shuffle kind	2018-04-26 13:48:33 +00:00
CMakeLists.txt	Consistently sort add_subdirectory calls in lib/Target/*/CMakeLists.txt	2018-04-23 12:49:34 +00:00
LLVMBuild.txt
SVEInstrFormats.td	[AArch64][SVE] Asm: Support for LDR/STR fill and spill instructions.	2018-05-02 13:32:39 +00:00