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f220e7cb76
We want to run the Machine Scheduler instead of the List Scheduler after RA. Checked with a performance run on a Power 9 machine with SPEC 2006 and while some benchmarks improved and others degraded the geomean was slightly improved with the Machine Scheduler. Differential Revision: https://reviews.llvm.org/D45265 llvm-svn: 336295
69 lines
2.2 KiB
LLVM
69 lines
2.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
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; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
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; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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@glob = common local_unnamed_addr global i16 0, align 2
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define signext i32 @test_iless(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: test_iless:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: sub r3, r4, r3
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; CHECK-NEXT: rldicl r3, r3, 1, 63
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; CHECK-NEXT: xori r3, r3, 1
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sle i16 %a, %b
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%conv2 = zext i1 %cmp to i32
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ret i32 %conv2
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}
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define signext i32 @test_iless_sext(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: test_iless_sext:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: sub r3, r4, r3
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; CHECK-NEXT: rldicl r3, r3, 1, 63
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; CHECK-NEXT: addi r3, r3, -1
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sle i16 %a, %b
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%sub = sext i1 %cmp to i32
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ret i32 %sub
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}
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define void @test_iless_store(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: test_iless_store:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
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; CHECK-NEXT: sub r3, r4, r3
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; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
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; CHECK-NEXT: rldicl r3, r3, 1, 63
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; CHECK-NEXT: xori r3, r3, 1
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; CHECK-NEXT: sth r3, 0(r4)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sle i16 %a, %b
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%conv3 = zext i1 %cmp to i16
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store i16 %conv3, i16* @glob, align 2
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ret void
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}
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define void @test_iless_sext_store(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: test_iless_sext_store:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
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; CHECK-NEXT: sub r3, r4, r3
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; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
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; CHECK-NEXT: rldicl r3, r3, 1, 63
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; CHECK-NEXT: addi r3, r3, -1
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; CHECK-NEXT: sth r3, 0(r4)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sle i16 %a, %b
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%conv3 = sext i1 %cmp to i16
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store i16 %conv3, i16* @glob, align 2
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ret void
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}
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