Oliver Stannard bc87e250e3 [AArch64] Extend single-operand FP insns to match Arm ARM (NFCI) ... The Armv8.3-A reference manual defines floating-point data-processing instructions with one source operand to have an opcode of 6 bits [20:15]. The current class in tablegen, BaseSingleOperandFPData, only allows [18:15]. This was ok because [20:19] could only be '00', with other encodings unallocated. Armv8.5-A brings in the FRINT group of instructions which use other values for these bits. This patch refactors the existing class a bit to allow using the full 6 bits of the opcode, as defined in the Arm ARM. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52474 llvm-svn: 343120		2018-09-26 15:42:47 +00:00
..
AsmParser	Revert r343112 as CallFrameString API change has broken lldb builds	2018-09-26 14:48:03 +00:00
Disassembler	[Target] Untangle disassemblers	2018-09-10 12:53:46 +00:00
InstPrinter	[AArch64][ARM] Armv8.4-A: Trace synchronization barrier instruction	2018-07-06 08:03:12 +00:00
MCTargetDesc	NFC: use bit_cast more in AArch64AddressingModes	2018-09-11 04:08:05 +00:00
TargetInfo
Utils	[MinGW] [AArch64] Add stubs for potential automatic dllimported variables	2018-09-04 20:56:21 +00:00
AArch64.h
AArch64.td	[ARM/AArch64][v8.5A] Add Armv8.5-A target	2018-09-26 12:48:21 +00:00
AArch64A53Fix835769.cpp
AArch64A57FPLoadBalancing.cpp
AArch64AdvSIMDScalarPass.cpp
AArch64AsmPrinter.cpp	[COFF] Hoist constant pool handling from X86AsmPrinter into AsmPrinter	2018-07-25 18:35:31 +00:00
AArch64CallingConvention.h
AArch64CallingConvention.td	[AArch64] Implement aarch64_vector_pcs codegen support.	2018-09-12 12:10:22 +00:00
AArch64CallLowering.cpp	[AArch64] Support adding X[8-15,18] registers as CSRs.	2018-09-22 22:17:50 +00:00
AArch64CallLowering.h	[GlobalISel] Rewrite CallLowering::lowerReturn to accept multiple VRegs per Value	2018-08-02 08:33:31 +00:00
AArch64CleanupLocalDynamicTLSPass.cpp
AArch64CollectLOH.cpp
AArch64CondBrTuning.cpp
AArch64ConditionalCompares.cpp
AArch64ConditionOptimizer.cpp
AArch64DeadRegisterDefinitionsPass.cpp
AArch64ExpandPseudoInsts.cpp	[AArch64] Add Tiny Code Model for AArch64	2018-08-22 11:31:39 +00:00
AArch64FalkorHWPFFix.cpp
AArch64FastISel.cpp	[AArch64] Support adding X[8-15,18] registers as CSRs.	2018-09-22 22:17:50 +00:00
AArch64FrameLowering.cpp	Revert r343112 as CallFrameString API change has broken lldb builds	2018-09-26 14:48:03 +00:00
AArch64FrameLowering.h
AArch64GenRegisterBankInfo.def
AArch64InstrAtomics.td
AArch64InstrFormats.td	[AArch64] Extend single-operand FP insns to match Arm ARM (NFCI)	2018-09-26 15:42:47 +00:00
AArch64InstrInfo.cpp	[MinGW] [AArch64] Add stubs for potential automatic dllimported variables	2018-09-04 20:56:21 +00:00
AArch64InstrInfo.h	[MachineOutliner][AArch64] Add support for saving LR to a register	2018-07-30 17:45:28 +00:00
AArch64InstrInfo.td	[ARM/AArch64][v8.5A] Add Armv8.5-A target	2018-09-26 12:48:21 +00:00
AArch64InstructionSelector.cpp	[AArch64] Add Tiny Code Model for AArch64	2018-08-22 11:31:39 +00:00
AArch64ISelDAGToDAG.cpp	[SDAG] Remove the reliance on MI's allocation strategy for	2018-08-14 23:30:32 +00:00
AArch64ISelLowering.cpp	[AArch64] Share search bookkeeping in combines. NFCI.	2018-09-25 15:30:22 +00:00
AArch64ISelLowering.h	[AtomicExpandPass]: Add a hook for custom cmpxchg expansion in IR	2018-09-19 14:51:42 +00:00
AArch64LegalizerInfo.cpp	[AArch64][GlobalISel] Make G_BLOCK_ADDR legal.	2018-07-31 00:08:56 +00:00
AArch64LegalizerInfo.h
AArch64LoadStoreOptimizer.cpp	[MI] Change the array of MachineMemOperand pointers to be	2018-08-16 21:30:05 +00:00
AArch64MachineFunctionInfo.h	Remove trailing space	2018-07-30 19:41:25 +00:00
AArch64MacroFusion.cpp	AArch64: Add FuseCryptoEOR fusion rules	2018-09-19 20:50:51 +00:00
AArch64MacroFusion.h
AArch64MCInstLower.cpp	[MinGW] [AArch64] Add stubs for potential automatic dllimported variables	2018-09-04 20:56:21 +00:00
AArch64MCInstLower.h
AArch64PBQPRegAlloc.cpp
AArch64PBQPRegAlloc.h
AArch64PerfectShuffle.h
AArch64PromoteConstant.cpp
AArch64RedundantCopyElimination.cpp	[CodeGen][AArch64] Use RegUnits to track register aliases. (NFC)	2018-05-23 17:49:38 +00:00
AArch64RegisterBankInfo.cpp
AArch64RegisterBankInfo.h
AArch64RegisterBanks.td
AArch64RegisterInfo.cpp	[Aarch64] Fix memcpy that was copying 4x too many bytes	2018-09-23 18:43:28 +00:00
AArch64RegisterInfo.h	[AArch64] Support adding X[8-15,18] registers as CSRs.	2018-09-22 22:17:50 +00:00
AArch64RegisterInfo.td	[AArch64][SVE] Asm: Add MOVPRFX instructions.	2018-07-30 15:42:46 +00:00
AArch64SchedA53.td
AArch64SchedA57.td
AArch64SchedA57WriteRes.td
AArch64SchedCyclone.td
AArch64SchedExynosM1.td	[ExynosM1][Sched] Fix resource usage in scheduling model.	2018-06-11 07:33:08 +00:00
AArch64SchedExynosM3.td
AArch64SchedFalkor.td
AArch64SchedFalkorDetails.td
AArch64SchedKryo.td
AArch64SchedKryoDetails.td
AArch64SchedThunderX2T99.td	[TableGen] Emit a fatal error on inconsistencies in resource units vs cycles.	2018-06-13 09:41:49 +00:00
AArch64SchedThunderX.td
AArch64Schedule.td
AArch64SelectionDAGInfo.cpp
AArch64SelectionDAGInfo.h
AArch64SIMDInstrOpt.cpp
AArch64StorePairSuppress.cpp
AArch64Subtarget.cpp	[AArch64] Support adding X[8-15,18] registers as CSRs.	2018-09-22 22:17:50 +00:00
AArch64Subtarget.h	[ARM/AArch64][v8.5A] Add Armv8.5-A target	2018-09-26 12:48:21 +00:00
AArch64SVEInstrInfo.td	[AArch64][SVE] Asm: Enable instructions to be prefixed.	2018-07-30 16:05:45 +00:00
AArch64SystemOperands.td	[AArch64][SVE] Asm: Add SVE System registers	2018-08-20 09:16:59 +00:00
AArch64TargetMachine.cpp	[AArch64] Add Tiny Code Model for AArch64	2018-08-22 11:31:39 +00:00
AArch64TargetMachine.h
AArch64TargetObjectFile.cpp	[AArch64] DWARF: do not generate AT_location for thread local	2018-08-01 23:46:49 +00:00
AArch64TargetObjectFile.h
AArch64TargetTransformInfo.cpp	Remove trailing space	2018-07-30 19:41:25 +00:00
AArch64TargetTransformInfo.h
CMakeLists.txt
LLVMBuild.txt
SVEInstrFormats.td	[AArch64][SVE] Asm: Enable instructions to be prefixed.	2018-07-30 16:05:45 +00:00