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One unusual feature of the z architecture is that the result of a previous load can be reused indefinitely for subsequent loads, even if a cache-coherent store to that location is performed by another CPU. A special serializing instruction must be used if you want to force a load to be reattempted. Since volatile loads are not supposed to be omitted in this way, we should insert a serializing instruction before each such load. The same goes for atomic loads. The patch implements this at the IR->DAG boundary, in a similar way to atomic fences. It is a no-op for targets other than SystemZ. llvm-svn: 196905 |
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.. | ||
CostTable.h | ||
Mangler.h | ||
Target.td | ||
TargetCallingConv.h | ||
TargetCallingConv.td | ||
TargetFrameLowering.h | ||
TargetInstrInfo.h | ||
TargetIntrinsicInfo.h | ||
TargetItinerary.td | ||
TargetJITInfo.h | ||
TargetLibraryInfo.h | ||
TargetLowering.h | ||
TargetLoweringObjectFile.h | ||
TargetMachine.h | ||
TargetOpcodes.h | ||
TargetOptions.h | ||
TargetRegisterInfo.h | ||
TargetSchedule.td | ||
TargetSelectionDAG.td | ||
TargetSelectionDAGInfo.h | ||
TargetSubtargetInfo.h |