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3bd9485a7c
Previous check-in message was: The patch adds missing registers and instructions to complete all the registers supported by the Sparc v8 manual. These are all co-processor registers, with the exception of the floating-point deferred-trap queue register. Although these will not be lowered automatically by any instructions, it allows the use of co-processor instructions implemented by inline-assembly. Code Reviewed at http://reviews.llvm.org/D17133, with the exception of a very small change in brace placement in SparcInstrInfo.td, which was formerly causing a problem in the disassembly of the %fq register. llvm-svn: 262135 |
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.. | ||
lit.local.cfg | ||
sparc64-alu-instructions.s | ||
sparc64-ctrl-instructions.s | ||
sparc-alu-instructions.s | ||
sparc-asm-errors.s | ||
sparc-assembly-exprs.s | ||
sparc-atomic-instructions.s | ||
sparc-coproc.s | ||
sparc-ctrl-instructions.s | ||
sparc-directive-xword.s | ||
sparc-directives.s | ||
sparc-fp-instructions.s | ||
sparc-little-endian.s | ||
sparc-mem-instructions.s | ||
sparc-nop-data.s | ||
sparc-pic.s | ||
sparc-relocations.s | ||
sparc-special-registers.s | ||
sparc-synthetic-instructions.s | ||
sparc-vis.s | ||
sparcv8-instructions.s | ||
sparcv9-atomic-instructions.s | ||
sparcv9-instructions.s |