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7df4542eb7
These are all co-processor registers, with the exception of the floating-point deferred-trap queue register. Although these will not be lowered automatically by any instructions, it allows the use of co-processor instructions implemented by inline-assembly. Code Reviewed at http://reviews.llvm.org/D17133, with the exception of a very small change in brace placement in SparcInstrInfo.td, which was formerly causing a problem in the disassembly of the %fq register. llvm-svn: 262133
57 lines
1.9 KiB
ArmAsm
57 lines
1.9 KiB
ArmAsm
! RUN: llvm-mc %s -arch=sparc -show-encoding | FileCheck %s
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! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s
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! CHECK: rd %y, %i0 ! encoding: [0xb1,0x40,0x00,0x00]
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rd %y, %i0
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! CHECK: rd %asr1, %i0 ! encoding: [0xb1,0x40,0x40,0x00]
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rd %asr1, %i0
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! CHECK: wr %i0, 5, %y ! encoding: [0x81,0x86,0x20,0x05]
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wr %i0, 5, %y
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! CHECK: wr %i0, %i1, %asr15 ! encoding: [0x9f,0x86,0x00,0x19]
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wr %i0, %i1, %asr15
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! CHECK: rd %asr15, %g0 ! encoding: [0x81,0x43,0xc0,0x00]
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rd %asr15, %g0
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! CHECK: rd %psr, %i0 ! encoding: [0xb1,0x48,0x00,0x00]
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rd %psr, %i0
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! CHECK: rd %wim, %i0 ! encoding: [0xb1,0x50,0x00,0x00]
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rd %wim, %i0
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! CHECK: rd %tbr, %i0 ! encoding: [0xb1,0x58,0x00,0x00]
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rd %tbr, %i0
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! CHECK: wr %i0, 5, %psr ! encoding: [0x81,0x8e,0x20,0x05]
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wr %i0, 5, %psr
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! CHECK: wr %i0, 5, %wim ! encoding: [0x81,0x96,0x20,0x05]
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wr %i0, 5, %wim
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! CHECK: wr %i0, 5, %tbr ! encoding: [0x81,0x9e,0x20,0x05]
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wr %i0, 5, %tbr
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! CHECK: rd %asr6, %i0 ! encoding: [0xb1,0x41,0x80,0x00]
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rd %fprs, %i0
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! CHECK: wr %i0, 7, %asr6 ! encoding: [0x8d,0x86,0x20,0x07]
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wr %i0, 7, %fprs
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! CHECK: ld [%g2+20], %fsr ! encoding: [0xc1,0x08,0xa0,0x14]
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ld [%g2 + 20],%fsr
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! CHECK: ld [%g2+%i5], %fsr ! encoding: [0xc1,0x08,0x80,0x1d]
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ld [%g2 + %i5],%fsr
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! CHECK: st %fsr, [%g2+20] ! encoding: [0xc1,0x28,0xa0,0x14]
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st %fsr,[%g2 + 20]
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! CHECK: st %fsr, [%g2+%i5] ! encoding: [0xc1,0x28,0x80,0x1d]
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st %fsr,[%g2 + %i5]
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! CHECK: std %fq, [%g6+%i2] ! encoding: [0xc1,0x31,0x80,0x1a]
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std %fq, [%g6 + %i2]
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