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4bf7d5872e
Upgrade of the IR text tests should be the only thing blocking making typed byval mandatory. Partially done through regex and partially manual.
39 lines
1.7 KiB
LLVM
39 lines
1.7 KiB
LLVM
; RUN: llc < %s -mcpu=cortex-a15 -verify-machineinstrs -arm-atomic-cfg-tidy=0 | FileCheck %s
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; Check a spill right after a function call with large struct byval is correctly
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; generated.
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; PR16393
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; We expect 4-byte spill and reload to be generated.
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; CHECK-LABEL: set_stored_macroblock_parameters:
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; CHECK: str r0, [sp, #{{[0-9]}}] @ 4-byte Spill
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; CHECK: @APP
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; CHECK: bl RestoreMVBlock8x8
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; CHECK: ldr r0, [sp, #{{[0-9]}}] @ 4-byte Reload
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target triple = "armv7l-unknown-linux-gnueabihf"
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%structN = type { i32, [16 x [16 x i32]], [16 x [16 x i32]], [16 x [16 x i32]], [3 x [16 x [16 x i32]]], [4 x i16], [4 x i8], [4 x i8], [4 x i8], [16 x [16 x i16]], [16 x [16 x i16]], [16 x [16 x i32]] }
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@tr8x8 = external global %structN, align 4
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@luma_transform_size_8x8_flag = external global i32, align 4
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; Function Attrs: nounwind
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define void @set_stored_macroblock_parameters(i16 %a0, i32 %a1) #1 {
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entry:
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%0 = load i32, i32* @luma_transform_size_8x8_flag, align 4
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tail call void asm sideeffect "", "~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11}"()
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tail call void @RestoreMVBlock8x8(i32 1, i32 2, %structN* byval(%structN) @tr8x8, i32 0)
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%arrayidx313 = getelementptr inbounds i8*, i8** null, i32 %0
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%1 = load i8*, i8** %arrayidx313, align 4
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%arrayidx314 = getelementptr inbounds i8, i8* %1, i32 0
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store i8 -1, i8* %arrayidx314, align 1
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ret void
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}
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; Function Attrs: nounwind
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declare void @RestoreMVBlock8x8(i32, i32, %structN* byval(%structN) nocapture, i32) #1
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attributes #1 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
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