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d4c615be8c
Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
41 lines
1.0 KiB
YAML
41 lines
1.0 KiB
YAML
# RUN: llc -march=hexagon -run-pass expand-condsets -o - %s -verify-machineinstrs | FileCheck %s
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# CHECK-LABEL: name: fred
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# Make sure that <def,read-undef> is accounted for when validating moves
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# during predication. In the code below, %2.isub_hi is invalidated
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# by the C2_mux instruction, and so predicating the A2_addi as an argument
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# to the C2_muxir should not happen.
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--- |
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define void @fred() { ret void }
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...
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---
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name: fred
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tracksRegLiveness: true
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registers:
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- { id: 0, class: predregs }
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- { id: 1, class: intregs }
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- { id: 2, class: doubleregs }
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- { id: 3, class: intregs }
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liveins:
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- { reg: '$p0', virtual-reg: '%0' }
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- { reg: '$r0', virtual-reg: '%1' }
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- { reg: '$d0', virtual-reg: '%2' }
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body: |
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bb.0:
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liveins: $r0, $d0, $p0
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%0 = COPY $p0
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%1 = COPY $r0
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%2 = COPY $d0
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; Check that this instruction is unchanged (remains unpredicated)
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; CHECK: %3:intregs = A2_addi %2.isub_hi, 1
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%3 = A2_addi %2.isub_hi, 1
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undef %2.isub_lo = C2_mux %0, %2.isub_lo, %1
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%2.isub_hi = C2_muxir %0, %3, 0
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...
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