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Currently tblgen cannot tell which operands in the operand list are results so it assumes the first one is a result. This is bad. Ideally we would fix this by separating results from inputs, e.g. (res R32:$dst), (ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding 'let noResults = 1' is the workaround to tell tblgen that the instruction does not produces a result. It works for now since tblgen does not support instructions which produce multiple results. llvm-svn: 25017 |
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.. | ||
.cvsignore | ||
DelaySlotFiller.cpp | ||
FPMover.cpp | ||
Makefile | ||
README.txt | ||
SparcV8.h | ||
SparcV8.td | ||
SparcV8AsmPrinter.cpp | ||
SparcV8InstrFormats.td | ||
SparcV8InstrInfo.cpp | ||
SparcV8InstrInfo.h | ||
SparcV8InstrInfo.td | ||
SparcV8ISelDAGToDAG.cpp | ||
SparcV8ISelSimple.cpp | ||
SparcV8RegisterInfo.cpp | ||
SparcV8RegisterInfo.h | ||
SparcV8RegisterInfo.td | ||
SparcV8TargetMachine.cpp | ||
SparcV8TargetMachine.h |
Meta TODO list: 1. Create a new DAG -> DAG instruction selector, by adding patterns to the instructions. 2. ??? 3. profit! To-do ----- * Keep the address of the constant pool in a register instead of forming its address all of the time. * We can fold small constant offsets into the %hi/%lo references to constant pool addresses as well.