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d4c615be8c
Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
43 lines
906 B
YAML
43 lines
906 B
YAML
# RUN: llc -run-pass=aarch64-expand-pseudo %s -o - | FileCheck %s
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--- |
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; ModuleID = 'simple.ll'
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source_filename = "simple.ll"
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target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64--linux-gnu"
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define i32 @test_mov_0() {
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ret i32 42
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}
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...
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---
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name: test_mov_0
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alignment: 2
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exposesReturnsTwice: false
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tracksRegLiveness: false
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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body: |
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bb.0 (%ir-block.0):
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$wzr = MOVi32imm 42
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$xzr = MOVi64imm 42
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RET_ReallyLR implicit killed $w0
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...
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# CHECK: bb.0
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# CHECK-NEXT: RET undef $lr
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