Qiu Chaofan 4e091a22bd [Legalizer] Fix some flags miss in vector results ... In some scalarize/split result methods (unary, binary, ...), flags in SDNode were not passed down, which may lead to unexpected results in unsafe float-point optimization. This patch fixes them. (maybe not complete) Reviewed By: spatel Differential Revision: https://reviews.llvm.org/D76832		2020-03-26 22:01:19 +08:00
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AArch64	[AArch64][SVE] Implement structured store intrinsics	2020-03-26 09:34:51 +00:00
AMDGPU	[AMDGPU] Fixed function traversal in attribute propagation	2020-03-25 18:47:09 -07:00
ARC
ARM	[ARM] Move ConstantIsland and LowOverheadLoops Passes.	2020-03-25 16:49:21 +01:00
AVR
BPF
Generic
Hexagon	Revert "Include static prof data when collecting loop BBs"	2020-03-24 09:41:16 -07:00
Inputs
Lanai
Mips
MIR
MSP430
NVPTX
PowerPC	[PowerPC] Improve the way legalize mul for v8i16 and add pattern to match mul + add	2020-03-26 04:46:49 +00:00
RISCV	[RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w	2020-03-20 09:42:24 +00:00
SPARC
SystemZ	[SystemZ] Improve foldMemoryOperandImpl()	2020-03-25 16:21:08 +01:00
Thumb	[DAGCombine] Skip PostInc combine with later users	2020-03-23 08:39:53 +00:00
Thumb2	[ARM] Sink splats to vector float instructions	2020-03-26 09:02:18 +00:00
VE
WebAssembly	[WebAssembly] Support swiftself and swifterror for WebAssembly target	2020-03-19 17:39:52 -07:00
WinCFGuard
WinEH
X86	[Legalizer] Fix some flags miss in vector results	2020-03-26 22:01:19 +08:00
XCore