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bd15210d03
The one place that uses these functions isn't particularly long/complicated, so it's easier to just have these inline at that location than trying to split it out into a true header. (in part also because of the use of the DEBUG macros, which make this not really a standalone header even if the static functions were made inline instead) llvm-svn: 324044
709 lines
27 KiB
C++
709 lines
27 KiB
C++
//===---- PPCReduceCRLogicals.cpp - Reduce CR Bit Logical operations ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===---------------------------------------------------------------------===//
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//
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// This pass aims to reduce the number of logical operations on bits in the CR
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// register. These instructions have a fairly high latency and only a single
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// pipeline at their disposal in modern PPC cores. Furthermore, they have a
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// tendency to occur in fairly small blocks where there's little opportunity
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// to hide the latency between the CR logical operation and its user.
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//
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//===---------------------------------------------------------------------===//
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#include "PPC.h"
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#include "PPCInstrInfo.h"
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#include "PPCTargetMachine.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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#define DEBUG_TYPE "ppc-reduce-cr-ops"
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STATISTIC(NumContainedSingleUseBinOps,
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"Number of single-use binary CR logical ops contained in a block");
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STATISTIC(NumToSplitBlocks,
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"Number of binary CR logical ops that can be used to split blocks");
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STATISTIC(TotalCRLogicals, "Number of CR logical ops.");
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STATISTIC(TotalNullaryCRLogicals,
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"Number of nullary CR logical ops (CRSET/CRUNSET).");
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STATISTIC(TotalUnaryCRLogicals, "Number of unary CR logical ops.");
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STATISTIC(TotalBinaryCRLogicals, "Number of CR logical ops.");
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STATISTIC(NumBlocksSplitOnBinaryCROp,
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"Number of blocks split on CR binary logical ops.");
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STATISTIC(NumNotSplitIdenticalOperands,
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"Number of blocks not split due to operands being identical.");
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STATISTIC(NumNotSplitChainCopies,
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"Number of blocks not split due to operands being chained copies.");
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STATISTIC(NumNotSplitWrongOpcode,
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"Number of blocks not split due to the wrong opcode.");
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namespace llvm {
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void initializePPCReduceCRLogicalsPass(PassRegistry&);
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}
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/// Given a basic block \p Successor that potentially contains PHIs, this
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/// function will look for any incoming values in the PHIs that are supposed to
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/// be coming from \p OrigMBB but whose definition is actually in \p NewMBB.
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/// Any such PHIs will be updated to reflect reality.
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static void updatePHIs(MachineBasicBlock *Successor, MachineBasicBlock *OrigMBB,
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MachineBasicBlock *NewMBB, MachineRegisterInfo *MRI) {
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for (auto &MI : Successor->instrs()) {
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if (!MI.isPHI())
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continue;
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// This is a really ugly-looking loop, but it was pillaged directly from
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// MachineBasicBlock::transferSuccessorsAndUpdatePHIs().
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for (unsigned i = 2, e = MI.getNumOperands() + 1; i != e; i += 2) {
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MachineOperand &MO = MI.getOperand(i);
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if (MO.getMBB() == OrigMBB) {
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// Check if the instruction is actualy defined in NewMBB.
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if (MI.getOperand(i - 1).isReg()) {
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MachineInstr *DefMI = MRI->getVRegDef(MI.getOperand(i - 1).getReg());
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if (DefMI->getParent() == NewMBB ||
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!OrigMBB->isSuccessor(Successor)) {
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MO.setMBB(NewMBB);
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break;
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}
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}
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}
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}
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}
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}
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/// Given a basic block \p Successor that potentially contains PHIs, this
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/// function will look for PHIs that have an incoming value from \p OrigMBB
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/// and will add the same incoming value from \p NewMBB.
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/// NOTE: This should only be used if \p NewMBB is an immediate dominator of
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/// \p OrigMBB.
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static void addIncomingValuesToPHIs(MachineBasicBlock *Successor,
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MachineBasicBlock *OrigMBB,
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MachineBasicBlock *NewMBB,
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MachineRegisterInfo *MRI) {
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assert(OrigMBB->isSuccessor(NewMBB) &&
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"NewMBB must be a sucessor of OrigMBB");
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for (auto &MI : Successor->instrs()) {
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if (!MI.isPHI())
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continue;
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// This is a really ugly-looking loop, but it was pillaged directly from
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// MachineBasicBlock::transferSuccessorsAndUpdatePHIs().
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for (unsigned i = 2, e = MI.getNumOperands() + 1; i != e; i += 2) {
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MachineOperand &MO = MI.getOperand(i);
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if (MO.getMBB() == OrigMBB) {
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MachineInstrBuilder MIB(*MI.getParent()->getParent(), &MI);
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MIB.addReg(MI.getOperand(i - 1).getReg()).addMBB(NewMBB);
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break;
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}
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}
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}
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}
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struct BlockSplitInfo {
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MachineInstr *OrigBranch;
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MachineInstr *SplitBefore;
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MachineInstr *SplitCond;
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bool InvertNewBranch;
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bool InvertOrigBranch;
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bool BranchToFallThrough;
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const MachineBranchProbabilityInfo *MBPI;
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MachineInstr *MIToDelete;
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MachineInstr *NewCond;
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bool allInstrsInSameMBB() {
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if (!OrigBranch || !SplitBefore || !SplitCond)
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return false;
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MachineBasicBlock *MBB = OrigBranch->getParent();
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if (SplitBefore->getParent() != MBB || SplitCond->getParent() != MBB)
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return false;
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if (MIToDelete && MIToDelete->getParent() != MBB)
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return false;
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if (NewCond && NewCond->getParent() != MBB)
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return false;
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return true;
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}
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};
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/// Splits a MachineBasicBlock to branch before \p SplitBefore. The original
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/// branch is \p OrigBranch. The target of the new branch can either be the same
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/// as the target of the original branch or the fallthrough successor of the
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/// original block as determined by \p BranchToFallThrough. The branch
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/// conditions will be inverted according to \p InvertNewBranch and
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/// \p InvertOrigBranch. If an instruction that previously fed the branch is to
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/// be deleted, it is provided in \p MIToDelete and \p NewCond will be used as
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/// the branch condition. The branch probabilities will be set if the
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/// MachineBranchProbabilityInfo isn't null.
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static bool splitMBB(BlockSplitInfo &BSI) {
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assert(BSI.allInstrsInSameMBB() &&
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"All instructions must be in the same block.");
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MachineBasicBlock *ThisMBB = BSI.OrigBranch->getParent();
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MachineFunction *MF = ThisMBB->getParent();
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MachineRegisterInfo *MRI = &MF->getRegInfo();
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assert(MRI->isSSA() && "Can only do this while the function is in SSA form.");
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if (ThisMBB->succ_size() != 2) {
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DEBUG(dbgs() << "Don't know how to handle blocks that don't have exactly"
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<< " two succesors.\n");
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return false;
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}
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const PPCInstrInfo *TII = MF->getSubtarget<PPCSubtarget>().getInstrInfo();
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unsigned OrigBROpcode = BSI.OrigBranch->getOpcode();
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unsigned InvertedOpcode =
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OrigBROpcode == PPC::BC
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? PPC::BCn
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: OrigBROpcode == PPC::BCn
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? PPC::BC
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: OrigBROpcode == PPC::BCLR ? PPC::BCLRn : PPC::BCLR;
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unsigned NewBROpcode = BSI.InvertNewBranch ? InvertedOpcode : OrigBROpcode;
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MachineBasicBlock *OrigTarget = BSI.OrigBranch->getOperand(1).getMBB();
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MachineBasicBlock *OrigFallThrough = OrigTarget == *ThisMBB->succ_begin()
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? *ThisMBB->succ_rbegin()
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: *ThisMBB->succ_begin();
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MachineBasicBlock *NewBRTarget =
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BSI.BranchToFallThrough ? OrigFallThrough : OrigTarget;
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BranchProbability ProbToNewTarget =
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!BSI.MBPI ? BranchProbability::getUnknown()
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: BSI.MBPI->getEdgeProbability(ThisMBB, NewBRTarget);
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// Create a new basic block.
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MachineBasicBlock::iterator InsertPoint = BSI.SplitBefore;
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const BasicBlock *LLVM_BB = ThisMBB->getBasicBlock();
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MachineFunction::iterator It = ThisMBB->getIterator();
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MachineBasicBlock *NewMBB = MF->CreateMachineBasicBlock(LLVM_BB);
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MF->insert(++It, NewMBB);
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// Move everything after SplitBefore into the new block.
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NewMBB->splice(NewMBB->end(), ThisMBB, InsertPoint, ThisMBB->end());
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NewMBB->transferSuccessors(ThisMBB);
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// Add the two successors to ThisMBB. The probabilities come from the
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// existing blocks if available.
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ThisMBB->addSuccessor(NewBRTarget, ProbToNewTarget);
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ThisMBB->addSuccessor(NewMBB, ProbToNewTarget.getCompl());
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// Add the branches to ThisMBB.
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BuildMI(*ThisMBB, ThisMBB->end(), BSI.SplitBefore->getDebugLoc(),
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TII->get(NewBROpcode))
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.addReg(BSI.SplitCond->getOperand(0).getReg())
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.addMBB(NewBRTarget);
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BuildMI(*ThisMBB, ThisMBB->end(), BSI.SplitBefore->getDebugLoc(),
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TII->get(PPC::B))
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.addMBB(NewMBB);
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if (BSI.MIToDelete)
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BSI.MIToDelete->eraseFromParent();
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// Change the condition on the original branch and invert it if requested.
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auto FirstTerminator = NewMBB->getFirstTerminator();
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if (BSI.NewCond) {
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assert(FirstTerminator->getOperand(0).isReg() &&
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"Can't update condition of unconditional branch.");
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FirstTerminator->getOperand(0).setReg(BSI.NewCond->getOperand(0).getReg());
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}
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if (BSI.InvertOrigBranch)
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FirstTerminator->setDesc(TII->get(InvertedOpcode));
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// If any of the PHIs in the successors of NewMBB reference values that
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// now come from NewMBB, they need to be updated.
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for (auto *Succ : NewMBB->successors()) {
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updatePHIs(Succ, ThisMBB, NewMBB, MRI);
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}
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addIncomingValuesToPHIs(NewBRTarget, ThisMBB, NewMBB, MRI);
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DEBUG(dbgs() << "After splitting, ThisMBB:\n"; ThisMBB->dump());
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DEBUG(dbgs() << "NewMBB:\n"; NewMBB->dump());
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DEBUG(dbgs() << "New branch-to block:\n"; NewBRTarget->dump());
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return true;
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}
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static bool isBinary(MachineInstr &MI) {
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return MI.getNumOperands() == 3;
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}
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static bool isNullary(MachineInstr &MI) {
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return MI.getNumOperands() == 1;
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}
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/// Given a CR logical operation \p CROp, branch opcode \p BROp as well as
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/// a flag to indicate if the first operand of \p CROp is used as the
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/// SplitBefore operand, determines whether either of the branches are to be
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/// inverted as well as whether the new target should be the original
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/// fall-through block.
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static void
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computeBranchTargetAndInversion(unsigned CROp, unsigned BROp, bool UsingDef1,
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bool &InvertNewBranch, bool &InvertOrigBranch,
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bool &TargetIsFallThrough) {
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// The conditions under which each of the output operands should be [un]set
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// can certainly be written much more concisely with just 3 if statements or
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// ternary expressions. However, this provides a much clearer overview to the
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// reader as to what is set for each <CROp, BROp, OpUsed> combination.
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if (BROp == PPC::BC || BROp == PPC::BCLR) {
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// Regular branches.
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switch (CROp) {
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default:
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llvm_unreachable("Don't know how to handle this CR logical.");
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case PPC::CROR:
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InvertNewBranch = false;
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InvertOrigBranch = false;
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TargetIsFallThrough = false;
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return;
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case PPC::CRAND:
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InvertNewBranch = true;
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InvertOrigBranch = false;
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TargetIsFallThrough = true;
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return;
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case PPC::CRNAND:
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InvertNewBranch = true;
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InvertOrigBranch = true;
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TargetIsFallThrough = false;
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return;
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case PPC::CRNOR:
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InvertNewBranch = false;
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InvertOrigBranch = true;
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TargetIsFallThrough = true;
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return;
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case PPC::CRORC:
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InvertNewBranch = UsingDef1;
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InvertOrigBranch = !UsingDef1;
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TargetIsFallThrough = false;
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return;
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case PPC::CRANDC:
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InvertNewBranch = !UsingDef1;
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InvertOrigBranch = !UsingDef1;
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TargetIsFallThrough = true;
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return;
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}
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} else if (BROp == PPC::BCn || BROp == PPC::BCLRn) {
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// Negated branches.
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switch (CROp) {
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default:
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llvm_unreachable("Don't know how to handle this CR logical.");
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case PPC::CROR:
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InvertNewBranch = true;
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InvertOrigBranch = false;
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TargetIsFallThrough = true;
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return;
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case PPC::CRAND:
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InvertNewBranch = false;
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InvertOrigBranch = false;
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TargetIsFallThrough = false;
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return;
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case PPC::CRNAND:
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InvertNewBranch = false;
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InvertOrigBranch = true;
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TargetIsFallThrough = true;
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return;
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case PPC::CRNOR:
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InvertNewBranch = true;
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InvertOrigBranch = true;
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TargetIsFallThrough = false;
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return;
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case PPC::CRORC:
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InvertNewBranch = !UsingDef1;
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InvertOrigBranch = !UsingDef1;
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TargetIsFallThrough = true;
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return;
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case PPC::CRANDC:
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InvertNewBranch = UsingDef1;
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InvertOrigBranch = !UsingDef1;
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TargetIsFallThrough = false;
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return;
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}
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} else
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llvm_unreachable("Don't know how to handle this branch.");
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}
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namespace {
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class PPCReduceCRLogicals : public MachineFunctionPass {
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public:
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static char ID;
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struct CRLogicalOpInfo {
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MachineInstr *MI;
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// FIXME: If chains of copies are to be handled, this should be a vector.
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std::pair<MachineInstr*, MachineInstr*> CopyDefs;
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std::pair<MachineInstr*, MachineInstr*> TrueDefs;
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unsigned IsBinary : 1;
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unsigned IsNullary : 1;
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unsigned ContainedInBlock : 1;
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unsigned FeedsISEL : 1;
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unsigned FeedsBR : 1;
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unsigned FeedsLogical : 1;
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unsigned SingleUse : 1;
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unsigned DefsSingleUse : 1;
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unsigned SubregDef1;
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unsigned SubregDef2;
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CRLogicalOpInfo() : MI(nullptr), IsBinary(0), IsNullary(0),
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ContainedInBlock(0), FeedsISEL(0), FeedsBR(0),
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FeedsLogical(0), SingleUse(0), DefsSingleUse(1),
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SubregDef1(0), SubregDef2(0) { }
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void dump();
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};
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private:
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const PPCInstrInfo *TII;
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MachineFunction *MF;
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MachineRegisterInfo *MRI;
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const MachineBranchProbabilityInfo *MBPI;
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// A vector to contain all the CR logical operations
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std::vector<CRLogicalOpInfo> AllCRLogicalOps;
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void initialize(MachineFunction &MFParm);
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void collectCRLogicals();
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bool handleCROp(CRLogicalOpInfo &CRI);
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bool splitBlockOnBinaryCROp(CRLogicalOpInfo &CRI);
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static bool isCRLogical(MachineInstr &MI) {
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unsigned Opc = MI.getOpcode();
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return Opc == PPC::CRAND || Opc == PPC::CRNAND || Opc == PPC::CROR ||
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Opc == PPC::CRXOR || Opc == PPC::CRNOR || Opc == PPC::CREQV ||
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Opc == PPC::CRANDC || Opc == PPC::CRORC || Opc == PPC::CRSET ||
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Opc == PPC::CRUNSET || Opc == PPC::CR6SET || Opc == PPC::CR6UNSET;
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}
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bool simplifyCode() {
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bool Changed = false;
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// Not using a range-based for loop here as the vector may grow while being
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// operated on.
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for (unsigned i = 0; i < AllCRLogicalOps.size(); i++)
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Changed |= handleCROp(AllCRLogicalOps[i]);
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return Changed;
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}
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public:
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PPCReduceCRLogicals() : MachineFunctionPass(ID) {
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initializePPCReduceCRLogicalsPass(*PassRegistry::getPassRegistry());
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}
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MachineInstr *lookThroughCRCopy(unsigned Reg, unsigned &Subreg,
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MachineInstr *&CpDef);
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bool runOnMachineFunction(MachineFunction &MF) override {
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if (skipFunction(MF.getFunction()))
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return false;
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// If the subtarget doesn't use CR bits, there's nothing to do.
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const PPCSubtarget &STI = MF.getSubtarget<PPCSubtarget>();
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if (!STI.useCRBits())
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return false;
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initialize(MF);
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collectCRLogicals();
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return simplifyCode();
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}
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CRLogicalOpInfo createCRLogicalOpInfo(MachineInstr &MI);
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addRequired<MachineBranchProbabilityInfo>();
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AU.addRequired<MachineDominatorTree>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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};
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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LLVM_DUMP_METHOD void PPCReduceCRLogicals::CRLogicalOpInfo::dump() {
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dbgs() << "CRLogicalOpMI: ";
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MI->dump();
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dbgs() << "IsBinary: " << IsBinary << ", FeedsISEL: " << FeedsISEL;
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dbgs() << ", FeedsBR: " << FeedsBR << ", FeedsLogical: ";
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dbgs() << FeedsLogical << ", SingleUse: " << SingleUse;
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dbgs() << ", DefsSingleUse: " << DefsSingleUse;
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dbgs() << ", SubregDef1: " << SubregDef1 << ", SubregDef2: ";
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dbgs() << SubregDef2 << ", ContainedInBlock: " << ContainedInBlock;
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if (!IsNullary) {
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dbgs() << "\nDefs:\n";
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TrueDefs.first->dump();
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}
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if (IsBinary)
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TrueDefs.second->dump();
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dbgs() << "\n";
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if (CopyDefs.first) {
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dbgs() << "CopyDef1: ";
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CopyDefs.first->dump();
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}
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if (CopyDefs.second) {
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dbgs() << "CopyDef2: ";
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CopyDefs.second->dump();
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}
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}
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#endif
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PPCReduceCRLogicals::CRLogicalOpInfo
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PPCReduceCRLogicals::createCRLogicalOpInfo(MachineInstr &MIParam) {
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CRLogicalOpInfo Ret;
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Ret.MI = &MIParam;
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// Get the defs
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if (isNullary(MIParam)) {
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Ret.IsNullary = 1;
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Ret.TrueDefs = std::make_pair(nullptr, nullptr);
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Ret.CopyDefs = std::make_pair(nullptr, nullptr);
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} else {
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MachineInstr *Def1 = lookThroughCRCopy(MIParam.getOperand(1).getReg(),
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Ret.SubregDef1, Ret.CopyDefs.first);
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Ret.DefsSingleUse &=
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MRI->hasOneNonDBGUse(Def1->getOperand(0).getReg());
|
|
Ret.DefsSingleUse &=
|
|
MRI->hasOneNonDBGUse(Ret.CopyDefs.first->getOperand(0).getReg());
|
|
assert(Def1 && "Must be able to find a definition of operand 1.");
|
|
if (isBinary(MIParam)) {
|
|
Ret.IsBinary = 1;
|
|
MachineInstr *Def2 = lookThroughCRCopy(MIParam.getOperand(2).getReg(),
|
|
Ret.SubregDef2,
|
|
Ret.CopyDefs.second);
|
|
Ret.DefsSingleUse &=
|
|
MRI->hasOneNonDBGUse(Def2->getOperand(0).getReg());
|
|
Ret.DefsSingleUse &=
|
|
MRI->hasOneNonDBGUse(Ret.CopyDefs.second->getOperand(0).getReg());
|
|
assert(Def2 && "Must be able to find a definition of operand 2.");
|
|
Ret.TrueDefs = std::make_pair(Def1, Def2);
|
|
} else {
|
|
Ret.TrueDefs = std::make_pair(Def1, nullptr);
|
|
Ret.CopyDefs.second = nullptr;
|
|
}
|
|
}
|
|
|
|
Ret.ContainedInBlock = 1;
|
|
// Get the uses
|
|
for (MachineInstr &UseMI :
|
|
MRI->use_nodbg_instructions(MIParam.getOperand(0).getReg())) {
|
|
unsigned Opc = UseMI.getOpcode();
|
|
if (Opc == PPC::ISEL || Opc == PPC::ISEL8)
|
|
Ret.FeedsISEL = 1;
|
|
if (Opc == PPC::BC || Opc == PPC::BCn || Opc == PPC::BCLR ||
|
|
Opc == PPC::BCLRn)
|
|
Ret.FeedsBR = 1;
|
|
Ret.FeedsLogical = isCRLogical(UseMI);
|
|
if (UseMI.getParent() != MIParam.getParent())
|
|
Ret.ContainedInBlock = 0;
|
|
}
|
|
Ret.SingleUse = MRI->hasOneNonDBGUse(MIParam.getOperand(0).getReg()) ? 1 : 0;
|
|
|
|
// We now know whether all the uses of the CR logical are in the same block.
|
|
if (!Ret.IsNullary) {
|
|
Ret.ContainedInBlock &=
|
|
(MIParam.getParent() == Ret.TrueDefs.first->getParent());
|
|
if (Ret.IsBinary)
|
|
Ret.ContainedInBlock &=
|
|
(MIParam.getParent() == Ret.TrueDefs.second->getParent());
|
|
}
|
|
DEBUG(Ret.dump());
|
|
if (Ret.IsBinary && Ret.ContainedInBlock && Ret.SingleUse) {
|
|
NumContainedSingleUseBinOps++;
|
|
if (Ret.FeedsBR && Ret.DefsSingleUse)
|
|
NumToSplitBlocks++;
|
|
}
|
|
return Ret;
|
|
}
|
|
|
|
/// Looks trhough a COPY instruction to the actual definition of the CR-bit
|
|
/// register and returns the instruction that defines it.
|
|
/// FIXME: This currently handles what is by-far the most common case:
|
|
/// an instruction that defines a CR field followed by a single copy of a bit
|
|
/// from that field into a virtual register. If chains of copies need to be
|
|
/// handled, this should have a loop until a non-copy instruction is found.
|
|
MachineInstr *PPCReduceCRLogicals::lookThroughCRCopy(unsigned Reg,
|
|
unsigned &Subreg,
|
|
MachineInstr *&CpDef) {
|
|
Subreg = -1;
|
|
if (!TargetRegisterInfo::isVirtualRegister(Reg))
|
|
return nullptr;
|
|
MachineInstr *Copy = MRI->getVRegDef(Reg);
|
|
CpDef = Copy;
|
|
if (!Copy->isCopy())
|
|
return Copy;
|
|
unsigned CopySrc = Copy->getOperand(1).getReg();
|
|
Subreg = Copy->getOperand(1).getSubReg();
|
|
if (!TargetRegisterInfo::isVirtualRegister(CopySrc)) {
|
|
const TargetRegisterInfo *TRI = &TII->getRegisterInfo();
|
|
// Set the Subreg
|
|
if (CopySrc == PPC::CR0EQ || CopySrc == PPC::CR6EQ)
|
|
Subreg = PPC::sub_eq;
|
|
if (CopySrc == PPC::CR0LT || CopySrc == PPC::CR6LT)
|
|
Subreg = PPC::sub_lt;
|
|
if (CopySrc == PPC::CR0GT || CopySrc == PPC::CR6GT)
|
|
Subreg = PPC::sub_gt;
|
|
if (CopySrc == PPC::CR0UN || CopySrc == PPC::CR6UN)
|
|
Subreg = PPC::sub_un;
|
|
// Loop backwards and return the first MI that modifies the physical CR Reg.
|
|
MachineBasicBlock::iterator Me = Copy, B = Copy->getParent()->begin();
|
|
while (Me != B)
|
|
if ((--Me)->modifiesRegister(CopySrc, TRI))
|
|
return &*Me;
|
|
return nullptr;
|
|
}
|
|
return MRI->getVRegDef(CopySrc);
|
|
}
|
|
|
|
void PPCReduceCRLogicals::initialize(MachineFunction &MFParam) {
|
|
MF = &MFParam;
|
|
MRI = &MF->getRegInfo();
|
|
TII = MF->getSubtarget<PPCSubtarget>().getInstrInfo();
|
|
MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
|
|
|
|
AllCRLogicalOps.clear();
|
|
}
|
|
|
|
/// Contains all the implemented transformations on CR logical operations.
|
|
/// For example, a binary CR logical can be used to split a block on its inputs,
|
|
/// a unary CR logical might be used to change the condition code on a
|
|
/// comparison feeding it. A nullary CR logical might simply be removable
|
|
/// if the user of the bit it [un]sets can be transformed.
|
|
bool PPCReduceCRLogicals::handleCROp(CRLogicalOpInfo &CRI) {
|
|
// We can definitely split a block on the inputs to a binary CR operation
|
|
// whose defs and (single) use are within the same block.
|
|
bool Changed = false;
|
|
if (CRI.IsBinary && CRI.ContainedInBlock && CRI.SingleUse && CRI.FeedsBR &&
|
|
CRI.DefsSingleUse) {
|
|
Changed = splitBlockOnBinaryCROp(CRI);
|
|
if (Changed)
|
|
NumBlocksSplitOnBinaryCROp++;
|
|
}
|
|
return Changed;
|
|
}
|
|
|
|
/// Splits a block that contains a CR-logical operation that feeds a branch
|
|
/// and whose operands are produced within the block.
|
|
/// Example:
|
|
/// %vr5<def> = CMPDI %vr2, 0; CRRC:%vr5 G8RC:%vr2
|
|
/// %vr6<def> = COPY %vr5:sub_eq; CRBITRC:%vr6 CRRC:%vr5
|
|
/// %vr7<def> = CMPDI %vr3, 0; CRRC:%vr7 G8RC:%vr3
|
|
/// %vr8<def> = COPY %vr7:sub_eq; CRBITRC:%vr8 CRRC:%vr7
|
|
/// %vr9<def> = CROR %vr6<kill>, %vr8<kill>; CRBITRC:%vr9,%vr6,%vr8
|
|
/// BC %vr9<kill>, <BB#2>; CRBITRC:%vr9
|
|
/// Becomes:
|
|
/// %vr5<def> = CMPDI %vr2, 0; CRRC:%vr5 G8RC:%vr2
|
|
/// %vr6<def> = COPY %vr5:sub_eq; CRBITRC:%vr6 CRRC:%vr5
|
|
/// BC %vr6<kill>, <BB#2>; CRBITRC:%vr6
|
|
///
|
|
/// %vr7<def> = CMPDI %vr3, 0; CRRC:%vr7 G8RC:%vr3
|
|
/// %vr8<def> = COPY %vr7:sub_eq; CRBITRC:%vr8 CRRC:%vr7
|
|
/// BC %vr9<kill>, <BB#2>; CRBITRC:%vr9
|
|
bool PPCReduceCRLogicals::splitBlockOnBinaryCROp(CRLogicalOpInfo &CRI) {
|
|
if (CRI.CopyDefs.first == CRI.CopyDefs.second) {
|
|
DEBUG(dbgs() << "Unable to split as the two operands are the same\n");
|
|
NumNotSplitIdenticalOperands++;
|
|
return false;
|
|
}
|
|
if (CRI.TrueDefs.first->isCopy() || CRI.TrueDefs.second->isCopy() ||
|
|
CRI.TrueDefs.first->isPHI() || CRI.TrueDefs.second->isPHI()) {
|
|
DEBUG(dbgs() << "Unable to split because one of the operands is a PHI or "
|
|
"chain of copies.\n");
|
|
NumNotSplitChainCopies++;
|
|
return false;
|
|
}
|
|
// Note: keep in sync with computeBranchTargetAndInversion().
|
|
if (CRI.MI->getOpcode() != PPC::CROR &&
|
|
CRI.MI->getOpcode() != PPC::CRAND &&
|
|
CRI.MI->getOpcode() != PPC::CRNOR &&
|
|
CRI.MI->getOpcode() != PPC::CRNAND &&
|
|
CRI.MI->getOpcode() != PPC::CRORC &&
|
|
CRI.MI->getOpcode() != PPC::CRANDC) {
|
|
DEBUG(dbgs() << "Unable to split blocks on this opcode.\n");
|
|
NumNotSplitWrongOpcode++;
|
|
return false;
|
|
}
|
|
DEBUG(dbgs() << "Splitting the following CR op:\n"; CRI.dump());
|
|
MachineBasicBlock::iterator Def1It = CRI.TrueDefs.first;
|
|
MachineBasicBlock::iterator Def2It = CRI.TrueDefs.second;
|
|
|
|
bool UsingDef1 = false;
|
|
MachineInstr *SplitBefore = &*Def2It;
|
|
for (auto E = CRI.MI->getParent()->end(); Def2It != E; ++Def2It) {
|
|
if (Def1It == Def2It) { // Def2 comes before Def1.
|
|
SplitBefore = &*Def1It;
|
|
UsingDef1 = true;
|
|
break;
|
|
}
|
|
}
|
|
|
|
DEBUG(dbgs() << "We will split the following block:\n";);
|
|
DEBUG(CRI.MI->getParent()->dump());
|
|
DEBUG(dbgs() << "Before instruction:\n"; SplitBefore->dump());
|
|
|
|
// Get the branch instruction.
|
|
MachineInstr *Branch =
|
|
MRI->use_nodbg_begin(CRI.MI->getOperand(0).getReg())->getParent();
|
|
|
|
// We want the new block to have no code in it other than the definition
|
|
// of the input to the CR logical and the CR logical itself. So we move
|
|
// those to the bottom of the block (just before the branch). Then we
|
|
// will split before the CR logical.
|
|
MachineBasicBlock *MBB = SplitBefore->getParent();
|
|
auto FirstTerminator = MBB->getFirstTerminator();
|
|
MachineBasicBlock::iterator FirstInstrToMove =
|
|
UsingDef1 ? CRI.TrueDefs.first : CRI.TrueDefs.second;
|
|
MachineBasicBlock::iterator SecondInstrToMove =
|
|
UsingDef1 ? CRI.CopyDefs.first : CRI.CopyDefs.second;
|
|
|
|
// The instructions that need to be moved are not guaranteed to be
|
|
// contiguous. Move them individually.
|
|
// FIXME: If one of the operands is a chain of (single use) copies, they
|
|
// can all be moved and we can still split.
|
|
MBB->splice(FirstTerminator, MBB, FirstInstrToMove);
|
|
if (FirstInstrToMove != SecondInstrToMove)
|
|
MBB->splice(FirstTerminator, MBB, SecondInstrToMove);
|
|
MBB->splice(FirstTerminator, MBB, CRI.MI);
|
|
|
|
unsigned Opc = CRI.MI->getOpcode();
|
|
bool InvertOrigBranch, InvertNewBranch, TargetIsFallThrough;
|
|
computeBranchTargetAndInversion(Opc, Branch->getOpcode(), UsingDef1,
|
|
InvertNewBranch, InvertOrigBranch,
|
|
TargetIsFallThrough);
|
|
MachineInstr *SplitCond =
|
|
UsingDef1 ? CRI.CopyDefs.second : CRI.CopyDefs.first;
|
|
DEBUG(dbgs() << "We will " << (InvertNewBranch ? "invert" : "copy"));
|
|
DEBUG(dbgs() << " the original branch and the target is the " <<
|
|
(TargetIsFallThrough ? "fallthrough block\n" : "orig. target block\n"));
|
|
DEBUG(dbgs() << "Original branch instruction: "; Branch->dump());
|
|
BlockSplitInfo BSI { Branch, SplitBefore, SplitCond, InvertNewBranch,
|
|
InvertOrigBranch, TargetIsFallThrough, MBPI, CRI.MI,
|
|
UsingDef1 ? CRI.CopyDefs.first : CRI.CopyDefs.second };
|
|
bool Changed = splitMBB(BSI);
|
|
// If we've split on a CR logical that is fed by a CR logical,
|
|
// recompute the source CR logical as it may be usable for splitting.
|
|
if (Changed) {
|
|
bool Input1CRlogical =
|
|
CRI.TrueDefs.first && isCRLogical(*CRI.TrueDefs.first);
|
|
bool Input2CRlogical =
|
|
CRI.TrueDefs.second && isCRLogical(*CRI.TrueDefs.second);
|
|
if (Input1CRlogical)
|
|
AllCRLogicalOps.push_back(createCRLogicalOpInfo(*CRI.TrueDefs.first));
|
|
if (Input2CRlogical)
|
|
AllCRLogicalOps.push_back(createCRLogicalOpInfo(*CRI.TrueDefs.second));
|
|
}
|
|
return Changed;
|
|
}
|
|
|
|
void PPCReduceCRLogicals::collectCRLogicals() {
|
|
for (MachineBasicBlock &MBB : *MF) {
|
|
for (MachineInstr &MI : MBB) {
|
|
if (isCRLogical(MI)) {
|
|
AllCRLogicalOps.push_back(createCRLogicalOpInfo(MI));
|
|
TotalCRLogicals++;
|
|
if (AllCRLogicalOps.back().IsNullary)
|
|
TotalNullaryCRLogicals++;
|
|
else if (AllCRLogicalOps.back().IsBinary)
|
|
TotalBinaryCRLogicals++;
|
|
else
|
|
TotalUnaryCRLogicals++;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
} // end annonymous namespace
|
|
|
|
INITIALIZE_PASS_BEGIN(PPCReduceCRLogicals, DEBUG_TYPE,
|
|
"PowerPC Reduce CR logical Operation", false, false)
|
|
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
|
|
INITIALIZE_PASS_END(PPCReduceCRLogicals, DEBUG_TYPE,
|
|
"PowerPC Reduce CR logical Operation", false, false)
|
|
|
|
char PPCReduceCRLogicals::ID = 0;
|
|
FunctionPass*
|
|
llvm::createPPCReduceCRLogicalsPass() { return new PPCReduceCRLogicals(); }
|