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e5c2597507
Return bool instead of void so that it is natural to put the calls into asserts. llvm-svn: 267033
112 lines
4.1 KiB
C++
112 lines
4.1 KiB
C++
//===- AArch64RegisterBankInfo.cpp -------------------------------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the targeting of the RegisterBankInfo class for
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/// AArch64.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#include "AArch64RegisterBankInfo.h"
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#include "AArch64InstrInfo.h" // For XXXRegClassID.
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#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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using namespace llvm;
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#ifndef LLVM_BUILD_GLOBAL_ISEL
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#error "You shouldn't build this"
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#endif
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AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
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: RegisterBankInfo(AArch64::NumRegisterBanks) {
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// Initialize the GPR bank.
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createRegisterBank(AArch64::GPRRegBankID, "GPR");
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// The GPR register bank is fully defined by all the registers in
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// GR64all + its subclasses.
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addRegBankCoverage(AArch64::GPRRegBankID, AArch64::GPR64allRegClassID, TRI);
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const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID);
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(void)RBGPR;
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assert(RBGPR.covers(*TRI.getRegClass(AArch64::GPR32RegClassID)) &&
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"Subclass not added?");
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assert(RBGPR.getSize() == 64 && "GPRs should hold up to 64-bit");
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// Initialize the FPR bank.
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createRegisterBank(AArch64::FPRRegBankID, "FPR");
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// The FPR register bank is fully defined by all the registers in
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// GR64all + its subclasses.
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addRegBankCoverage(AArch64::FPRRegBankID, AArch64::QQQQRegClassID, TRI);
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const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID);
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(void)RBFPR;
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assert(RBFPR.covers(*TRI.getRegClass(AArch64::QQRegClassID)) &&
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"Subclass not added?");
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assert(RBFPR.covers(*TRI.getRegClass(AArch64::FPR64RegClassID)) &&
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"Subclass not added?");
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assert(RBFPR.getSize() == 512 &&
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"FPRs should hold up to 512-bit via QQQQ sequence");
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// Initialize the CCR bank.
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createRegisterBank(AArch64::CCRRegBankID, "CCR");
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addRegBankCoverage(AArch64::CCRRegBankID, AArch64::CCRRegClassID, TRI);
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const RegisterBank &RBCCR = getRegBank(AArch64::CCRRegBankID);
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(void)RBCCR;
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assert(RBCCR.covers(*TRI.getRegClass(AArch64::CCRRegClassID)) &&
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"Class not added?");
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assert(RBCCR.getSize() == 32 && "CCR should hold up to 32-bit");
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assert(verify(TRI) && "Invalid register bank information");
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}
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unsigned AArch64RegisterBankInfo::copyCost(const RegisterBank &A,
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const RegisterBank &B) const {
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// What do we do with different size?
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// copy are same size.
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// Will introduce other hooks for different size:
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// * extract cost.
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// * build_sequence cost.
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return 0;
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}
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const RegisterBank &AArch64RegisterBankInfo::getRegBankFromRegClass(
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const TargetRegisterClass &RC) const {
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switch (RC.getID()) {
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case AArch64::FPR8RegClassID:
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case AArch64::FPR16RegClassID:
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case AArch64::FPR32RegClassID:
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case AArch64::FPR64RegClassID:
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case AArch64::FPR128RegClassID:
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case AArch64::FPR128_loRegClassID:
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case AArch64::DDRegClassID:
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case AArch64::DDDRegClassID:
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case AArch64::DDDDRegClassID:
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case AArch64::QQRegClassID:
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case AArch64::QQQRegClassID:
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case AArch64::QQQQRegClassID:
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return getRegBank(AArch64::FPRRegBankID);
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case AArch64::GPR32commonRegClassID:
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case AArch64::GPR32RegClassID:
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case AArch64::GPR32spRegClassID:
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case AArch64::GPR32sponlyRegClassID:
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case AArch64::GPR32allRegClassID:
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case AArch64::GPR64commonRegClassID:
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case AArch64::GPR64RegClassID:
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case AArch64::GPR64spRegClassID:
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case AArch64::GPR64sponlyRegClassID:
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case AArch64::GPR64allRegClassID:
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case AArch64::tcGPR64RegClassID:
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case AArch64::WSeqPairsClassRegClassID:
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case AArch64::XSeqPairsClassRegClassID:
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return getRegBank(AArch64::GPRRegBankID);
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case AArch64::CCRRegClassID:
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return getRegBank(AArch64::CCRRegBankID);
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default:
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llvm_unreachable("Register class not supported");
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}
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}
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