Sanjay Patel 94e71f929a [x86] allow insert/extract when matching horizontal ops ... Previously, we limited this transform to cases where the extraction into the build vector happens from vectors of the same type as the build vector, but that's not required. There's a slight potential regression seen in the AVX512 result for phadd -- we're using the 256-bit flavor of the instruction now even though the 128-bit subset is sufficient. The same problem could already be seen in the AVX2 result. Follow-up patches will attempt to narrow that back down. llvm-svn: 350928		2019-01-11 14:27:59 +00:00
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AArch64	[AArch64] Fix operation actions for FP16 vector intrinsics	2019-01-10 15:02:37 +00:00
AMDGPU	[AMDGPU] Fix dwordx3/southern-islands failures.	2019-01-10 16:21:08 +00:00
ARC
ARM
AVR
BPF
Generic
Hexagon
Inputs
Lanai
Mips	[llvm-objdump] - Implement -z/--disassemble-zeroes.	2019-01-10 14:55:26 +00:00
MIR
MSP430	[MSP430] Add missing instruction forms	2019-01-10 22:54:53 +00:00
Nios2
NVPTX
PowerPC	Recommit "[PowerPC] Fix assert from machine verify pass that unmatched register class about fcmp selection in fast-isel"	2019-01-10 06:20:14 +00:00
RISCV
SPARC
SystemZ
Thumb
Thumb2	[ARM] Size reduce teq to eors	2019-01-10 08:36:33 +00:00
WebAssembly	[WebAssembly] Fix stack pointer store check in RegStackify	2019-01-10 23:12:07 +00:00
WinCFGuard
WinEH
X86	[x86] allow insert/extract when matching horizontal ops	2019-01-11 14:27:59 +00:00
XCore