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114 lines
3.8 KiB
LLVM
114 lines
3.8 KiB
LLVM
; RUN: llc -mtriple amdgcn--amdhsa -mcpu=fiji -amdgpu-scalarize-global-loads=true -verify-machineinstrs < %s | FileCheck %s
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; CHECK-LABEL: %bb11
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; Load from %arg in a Loop body has alias store
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; CHECK: flat_load_dword
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; CHECK-LABEL: %bb20
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; CHECK: flat_store_dword
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; #####################################################################
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; CHECK-LABEL: %bb22
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; Load from %arg has alias store in Loop
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; CHECK: flat_load_dword
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; #####################################################################
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; Load from %arg1 has no-alias store in Loop - arg1[i+1] never alias arg1[i]
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; CHECK: s_load_dword
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define amdgpu_kernel void @cfg(i32 addrspace(1)* nocapture readonly %arg, i32 addrspace(1)* nocapture %arg1, i32 %arg2) #0 {
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bb:
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%tmp = sext i32 %arg2 to i64
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%tmp3 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp
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%tmp4 = load i32, i32 addrspace(1)* %tmp3, align 4, !tbaa !0
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%tmp5 = icmp sgt i32 %tmp4, 0
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br i1 %tmp5, label %bb6, label %bb8
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bb6: ; preds = %bb
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br label %bb11
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bb7: ; preds = %bb22
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br label %bb8
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bb8: ; preds = %bb7, %bb
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%tmp9 = phi i32 [ 0, %bb ], [ %tmp30, %bb7 ]
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%tmp10 = getelementptr inbounds i32, i32 addrspace(1)* %arg1, i64 %tmp
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store i32 %tmp9, i32 addrspace(1)* %tmp10, align 4, !tbaa !0
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ret void
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bb11: ; preds = %bb22, %bb6
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%tmp12 = phi i32 [ %tmp30, %bb22 ], [ 0, %bb6 ]
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%tmp13 = phi i32 [ %tmp25, %bb22 ], [ 0, %bb6 ]
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%tmp14 = srem i32 %tmp13, %arg2
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%tmp15 = sext i32 %tmp14 to i64
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%tmp16 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp15
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%tmp17 = load i32, i32 addrspace(1)* %tmp16, align 4, !tbaa !0
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%tmp18 = icmp sgt i32 %tmp17, 100
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%tmp19 = sext i32 %tmp13 to i64
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br i1 %tmp18, label %bb20, label %bb22
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bb20: ; preds = %bb11
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%tmp21 = getelementptr inbounds i32, i32 addrspace(1)* %arg1, i64 %tmp19
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store i32 0, i32 addrspace(1)* %tmp21, align 4, !tbaa !0
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br label %bb22
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bb22: ; preds = %bb20, %bb11
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%tmp23 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp19
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%tmp24 = load i32, i32 addrspace(1)* %tmp23, align 4, !tbaa !0
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%tmp25 = add nuw nsw i32 %tmp13, 1
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%tmp26 = sext i32 %tmp25 to i64
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%tmp27 = getelementptr inbounds i32, i32 addrspace(1)* %arg1, i64 %tmp26
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%tmp28 = load i32, i32 addrspace(1)* %tmp27, align 4, !tbaa !0
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%tmp29 = add i32 %tmp24, %tmp12
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%tmp30 = add i32 %tmp29, %tmp28
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%tmp31 = icmp eq i32 %tmp25, %tmp4
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br i1 %tmp31, label %bb7, label %bb11
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}
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; one more test to ensure that aliasing store after the load
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; is considered clobbering if load parent block is the same
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; as a loop header block.
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; CHECK-LABEL: %bb1
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; Load from %arg has alias store that is after the load
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; but is considered clobbering because of the loop.
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; CHECK: flat_load_dword
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define amdgpu_kernel void @cfg_selfloop(i32 addrspace(1)* nocapture readonly %arg, i32 addrspace(1)* nocapture %arg1, i32 %arg2) #0 {
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bb:
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br label %bb1
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bb2:
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ret void
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bb1:
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%tmp13 = phi i32 [ %tmp25, %bb1 ], [ 0, %bb ]
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%tmp14 = srem i32 %tmp13, %arg2
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%tmp15 = sext i32 %tmp14 to i64
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%tmp16 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp15
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%tmp17 = load i32, i32 addrspace(1)* %tmp16, align 4, !tbaa !0
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%tmp19 = sext i32 %tmp13 to i64
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%tmp21 = getelementptr inbounds i32, i32 addrspace(1)* %arg1, i64 %tmp19
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store i32 %tmp17, i32 addrspace(1)* %tmp21, align 4, !tbaa !0
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%tmp25 = add nuw nsw i32 %tmp13, 1
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%tmp31 = icmp eq i32 %tmp25, 100
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br i1 %tmp31, label %bb2, label %bb1
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}
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attributes #0 = { "target-cpu"="fiji" }
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!0 = !{!1, !1, i64 0}
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!1 = !{!"int", !2, i64 0}
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!2 = !{!"omnipotent char", !3, i64 0}
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!3 = !{!"Simple C/C++ TBAA"}
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