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c21c095194
This commit modifies the way the machine basic blocks are serialized - now the
machine basic blocks are serialized using a custom syntax instead of relying on
YAML primitives. Instead of using YAML mappings to represent the individual
machine basic blocks in a machine function's body, the new syntax uses a single
YAML block scalar which contains all of the machine basic blocks and
instructions for that function.
This is an example of a function's body that uses the old syntax:
body:
- id: 0
name: entry
instructions:
- '%eax = MOV32r0 implicit-def %eflags'
- 'RETQ %eax'
...
The same body is now written like this:
body: |
bb.0.entry:
%eax = MOV32r0 implicit-def %eflags
RETQ %eax
...
This syntax change is motivated by the fact that the bundled machine
instructions didn't map that well to the old syntax which was using a single
YAML sequence to store all of the machine instructions in a block. The bundled
machine instructions internally use flags like BundledPred and BundledSucc to
determine the bundles, and serializing them as MI flags using the old syntax
would have had a negative impact on the readability and the ease of editing
for MIR files. The new syntax allows me to serialize the bundled machine
instructions using a block construct without relying on the internal flags,
for example:
BUNDLE implicit-def dead %itstate, implicit-def %s1 ... {
t2IT 1, 24, implicit-def %itstate
%s1 = VMOVS killed %s0, 1, killed %cpsr, implicit killed %itstate
}
This commit also converts the MIR testcases to the new syntax. I developed
a script that can convert from the old syntax to the new one. I will post the
script on the llvm-commits mailing list in the thread for this commit.
llvm-svn: 244982
38 lines
838 B
YAML
38 lines
838 B
YAML
# RUN: llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s | FileCheck %s
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# This test ensures that the MIR parser parses machine function's liveins
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# correctly.
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--- |
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define i32 @test(i32 %a, i32 %b) {
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body:
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%c = add i32 %a, %b
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ret i32 %c
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}
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...
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---
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name: test
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isSSA: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gr32 }
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- { id: 1, class: gr32 }
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- { id: 2, class: gr32 }
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# CHECK: liveins:
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# CHECK-NEXT: - { reg: '%edi', virtual-reg: '%0' }
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# CHECK-NEXT: - { reg: '%esi', virtual-reg: '%1' }
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liveins:
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- { reg: '%edi', virtual-reg: '%0' }
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- { reg: '%esi', virtual-reg: '%1' }
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body: |
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bb.0.body:
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liveins: %edi, %esi
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%1 = COPY %esi
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%0 = COPY %edi
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%2 = ADD32rr %0, %1, implicit-def dead %eflags
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%eax = COPY %2
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RETQ %eax
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...
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