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https://github.com/RPCS3/llvm-mirror.git
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74a8dfdced
Summary: This patch introduces command-line support for the Armv8.6-a architecture and assembly support for BFloat16. Details can be found https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-architecture-developments-armv8-6-a in addition to the GCC patch for the 8..6-a CLI: https://gcc.gnu.org/legacy-ml/gcc-patches/2019-11/msg02647.html In detail this patch - march options for armv8.6-a - BFloat16 assembly This is part of a patch series, starting with command-line and Bfloat16 assembly support. The subsequent patches will upstream intrinsics support for BFloat16, followed by Matrix Multiplication and the remaining Virtualization features of the armv8.6-a architecture. Based on work by: - labrinea - MarkMurrayARM - Luke Cheeseman - Javed Asbar - Mikhail Maltsev - Luke Geeson Reviewers: SjoerdMeijer, craig.topper, rjmccall, jfb, LukeGeeson Reviewed By: SjoerdMeijer Subscribers: stuij, kristof.beyls, hiraditya, dexonsmith, danielkiss, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D76062
135 lines
4.9 KiB
ArmAsm
135 lines
4.9 KiB
ArmAsm
// RUN: not llvm-mc -o - -triple arm -mattr=+v8.6a -show-encoding %s 2>&1 | FileCheck %s
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vfmat.bf16 d0, d0, d0
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vfmat.bf16 d0, d0, q0
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vfmat.bf16 d0, q0, d0
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vfmat.bf16 q0, d0, d0
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vfmat.bf16 q0, q0, d0
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vfmat.bf16 q0, d0, q0
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vfmat.bf16 d0, q0, q0
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vfmat.bf16 q0, q0, q0[3]
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vfmat.bf16 q0, q0, q0[3]
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vfmat.bf16 q0, d0, d0[0]
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vfmat.bf16 d0, q0, d0[0]
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vfmat.bf16 q0, d0, d0[9]
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vfmab.bf16 d0, d0, d0
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vfmab.bf16 d0, d0, q0
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vfmab.bf16 d0, q0, d0
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vfmab.bf16 q0, d0, d0
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vfmab.bf16 q0, q0, d0
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vfmab.bf16 q0, d0, q0
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vfmab.bf16 d0, q0, q0
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vfmab.bf16 q0, q0, q0[3]
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vfmab.bf16 q0, q0, q0[3]
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vfmab.bf16 q0, d0, d0[0]
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vfmab.bf16 d0, q0, d0[0]
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vfmab.bf16 q0, d0, d0[9]
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//CHECK:error: invalid instruction
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//CHECK-NEXT:vfmat.bf16 d0, d0, d0
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//CHECK-NEXT:^
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//CHECK-NEXT:error: invalid instruction
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//CHECK-NEXT:vfmat.bf16 d0, d0, q0
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//CHECK-NEXT:^
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//CHECK-NEXT:error: invalid instruction
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//CHECK-NEXT:vfmat.bf16 d0, q0, d0
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//CHECK-NEXT:^
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//CHECK-NEXT:error: invalid instruction
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//CHECK-NEXT:vfmat.bf16 q0, d0, d0
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//CHECK-NEXT:^
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//CHECK-NEXT:error: invalid instruction, any one of the following would fix this:
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//CHECK-NEXT:vfmat.bf16 q0, q0, d0
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//CHECK-NEXT:^
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//CHECK-NEXT:note: too few operands for instruction
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//CHECK-NEXT:vfmat.bf16 q0, q0, d0
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//CHECK-NEXT: ^
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//CHECK-NEXT:note: operand must be a register in range [q0, q15]
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//CHECK-NEXT:vfmat.bf16 q0, q0, d0
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//CHECK-NEXT: ^
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//CHECK-NEXT:error: operand must be a register in range [q0, q15]
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//CHECK-NEXT:vfmat.bf16 q0, d0, q0
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//CHECK-NEXT: ^
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//CHECK-NEXT:error: operand must be a register in range [q0, q15]
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//CHECK-NEXT:vfmat.bf16 d0, q0, q0
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//CHECK-NEXT: ^
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//CHECK-NEXT:error: invalid instruction, any one of the following would fix this:
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//CHECK-NEXT:vfmat.bf16 q0, q0, q0[3]
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//CHECK-NEXT:^
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//CHECK-NEXT:note: operand must be a register in range [d0, d7]
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//CHECK-NEXT:vfmat.bf16 q0, q0, q0[3]
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//CHECK-NEXT: ^
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//CHECK-NEXT:note: too many operands for instruction
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//CHECK-NEXT:vfmat.bf16 q0, q0, q0[3]
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//CHECK-NEXT: ^
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//CHECK-NEXT:error: invalid instruction, any one of the following would fix this:
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//CHECK-NEXT:vfmat.bf16 q0, q0, q0[3]
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//CHECK-NEXT:^
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//CHECK-NEXT:note: operand must be a register in range [d0, d7]
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//CHECK-NEXT:vfmat.bf16 q0, q0, q0[3]
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//CHECK-NEXT: ^
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//CHECK-NEXT:note: too many operands for instruction
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//CHECK-NEXT:vfmat.bf16 q0, q0, q0[3]
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//CHECK-NEXT: ^
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//CHECK-NEXT:error: operand must be a register in range [q0, q15]
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//CHECK-NEXT:vfmat.bf16 q0, d0, d0[0]
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//CHECK-NEXT: ^
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//CHECK-NEXT:error: operand must be a register in range [q0, q15]
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//CHECK-NEXT:vfmat.bf16 d0, q0, d0[0]
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//CHECK-NEXT: ^
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//CHECK-NEXT:error: invalid instruction
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//CHECK-NEXT:vfmat.bf16 q0, d0, d0[9]
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//CHECK-NEXT:^
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//CHECK-NEXT:error: invalid instruction
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//CHECK-NEXT:vfmab.bf16 d0, d0, d0
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//CHECK-NEXT:^
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//CHECK-NEXT:error: invalid instruction
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//CHECK-NEXT:vfmab.bf16 d0, d0, q0
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//CHECK-NEXT:^
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//CHECK-NEXT:error: invalid instruction
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//CHECK-NEXT:vfmab.bf16 d0, q0, d0
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//CHECK-NEXT:^
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//CHECK-NEXT:error: invalid instruction
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//CHECK-NEXT:vfmab.bf16 q0, d0, d0
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//CHECK-NEXT:^
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//CHECK-NEXT:error: invalid instruction, any one of the following would fix this:
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//CHECK-NEXT:vfmab.bf16 q0, q0, d0
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//CHECK-NEXT:^
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//CHECK-NEXT:note: too few operands for instruction
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//CHECK-NEXT:vfmab.bf16 q0, q0, d0
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//CHECK-NEXT: ^
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//CHECK-NEXT:note: operand must be a register in range [q0, q15]
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//CHECK-NEXT:vfmab.bf16 q0, q0, d0
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//CHECK-NEXT: ^
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//CHECK-NEXT:error: operand must be a register in range [q0, q15]
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//CHECK-NEXT:vfmab.bf16 q0, d0, q0
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//CHECK-NEXT: ^
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//CHECK-NEXT:error: operand must be a register in range [q0, q15]
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//CHECK-NEXT:vfmab.bf16 d0, q0, q0
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//CHECK-NEXT: ^
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//CHECK-NEXT:error: invalid instruction, any one of the following would fix this:
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//CHECK-NEXT:vfmab.bf16 q0, q0, q0[3]
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//CHECK-NEXT:^
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//CHECK-NEXT:note: operand must be a register in range [d0, d7]
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//CHECK-NEXT:vfmab.bf16 q0, q0, q0[3]
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//CHECK-NEXT: ^
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//CHECK-NEXT:note: too many operands for instruction
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//CHECK-NEXT:vfmab.bf16 q0, q0, q0[3]
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//CHECK-NEXT: ^
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//CHECK-NEXT:error: invalid instruction, any one of the following would fix this:
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//CHECK-NEXT:vfmab.bf16 q0, q0, q0[3]
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//CHECK-NEXT:^
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//CHECK-NEXT:note: operand must be a register in range [d0, d7]
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//CHECK-NEXT:vfmab.bf16 q0, q0, q0[3]
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//CHECK-NEXT: ^
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//CHECK-NEXT:note: too many operands for instruction
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//CHECK-NEXT:vfmab.bf16 q0, q0, q0[3]
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//CHECK-NEXT: ^
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//CHECK-NEXT:error: operand must be a register in range [q0, q15]
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//CHECK-NEXT:vfmab.bf16 q0, d0, d0[0]
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//CHECK-NEXT: ^
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//CHECK-NEXT:error: operand must be a register in range [q0, q15]
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//CHECK-NEXT:vfmab.bf16 d0, q0, d0[0]
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//CHECK-NEXT: ^
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//CHECK-NEXT:error: invalid instruction
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//CHECK-NEXT:vfmab.bf16 q0, d0, d0[9]
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