mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-26 04:32:44 +01:00
92ee2a8454
Make the non-tied register operand names line up with what the base class encoding handler expects. rdar://11157236 llvm-svn: 153766
8 lines
263 B
ArmAsm
8 lines
263 B
ArmAsm
@ RUN: llvm-mc -mcpu=cortex-a8 -triple armv7-apple-darwin -show-encoding < %s | FileCheck %s
|
|
|
|
vswp d1, d2
|
|
vswp q1, q2
|
|
|
|
@ CHECK: vswp d1, d2 @ encoding: [0x02,0x10,0xb2,0xf3]
|
|
@ CHECK: vswp q1, q2 @ encoding: [0x44,0x20,0xb2,0xf3]
|