Renato Golin 57cdb5383f [ARM] Saturation instructions are DSP-only ... The saturation instructions appeared in v6T2, with DSP extensions, but they were being accepted / generated on any, with the new introduction of the saturation detection in the back-end. This commit restricts the usage to DSP-enable only cores. Fixes PR28607. llvm-svn: 276701		2016-07-25 22:25:25 +00:00
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AArch64	AArch64: TableGenerate system instruction operands.	2016-07-05 21:23:04 +00:00
AMDGPU	[AMDGPU] fix ds_swizzle_b32 opcode for VI (bz 28371)	2016-07-08 15:12:46 +00:00
ARM	[ARM] Saturation instructions are DSP-only	2016-07-25 22:25:25 +00:00
Hexagon	[Hexagon] Treat all conditional branches as predicted (not-taken by default)	2016-05-09 18:22:07 +00:00
Lanai	[lanai] Add Lanai backend.	2016-03-28 13:09:54 +00:00
Mips	[mips][microMIPS] Implement SLT, SLTI, SLTIU, SLTU microMIPS32r6 instructions	2016-07-22 07:18:33 +00:00
PowerPC	This reverts commit r265505.	2016-04-28 20:00:42 +00:00
Sparc	This change adds co-processor condition branching and conditional traps to the Sparc back-end.	2016-03-09 18:20:21 +00:00
SystemZ	[SystemZ] Recognize Load On Condition Immediate (LOCHI/LOGHI) opportunities	2016-07-11 18:45:03 +00:00
X86	Add new flag and intrinsic support for MWAITX and MONITORX instructions	2016-05-18 11:59:12 +00:00
XCore