mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-29 23:12:55 +01:00
d535cd7ed5
The trouble as in ARMAsmParser, in ParseInstruction method. It assumes that ARM::R12 + 1 == ARM::SP. It is wrong, since ARM::<Register> codes are generated by tablegen and actually could be any random numbers. llvm-svn: 205524
10 lines
306 B
ArmAsm
10 lines
306 B
ArmAsm
// PR19320
|
|
// RUN: llvm-mc -triple=armv7-linux-gnueabi -show-encoding < %s | FileCheck %s
|
|
.text
|
|
|
|
// CHECK: ldrd r12, sp, [r0, #32] @ encoding: [0xd0,0xc2,0xc0,0xe1]
|
|
ldrd r12, [r0, #32]
|
|
|
|
// CHECK: strd r12, sp, [r0, #32] @ encoding: [0xf0,0xc2,0xc0,0xe1]
|
|
strd r12, [r0, #32]
|