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8f83ef0f5e
Patch [4/5] in a series to add assembler/disassembler support for AArch64 SVE unpredicated ADD/SUB instructions. We add SVE as unsupported feature for CPUs that don't have SVE to prevent errors from scheduler models saying it lacks information for these instructions. Patch by Sander De Smalen. Reviewed by: rengolin Differential Revision: https://reviews.llvm.org/D39090 llvm-svn: 317582
136 lines
6.0 KiB
TableGen
136 lines
6.0 KiB
TableGen
//==- AArch64SchedKryo.td - Qualcomm Kryo Scheduling Defs ---*- tablegen -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the machine model for Qualcomm Kryo to support
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// instruction scheduling and other instruction cost heuristics.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// The issue width is set to five, matching the five issue queues for expanded
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// uops. Now, the latency spreadsheet has information based on fragmented uops,
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// but these do not actually take up an issue queue.
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def KryoModel : SchedMachineModel {
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let IssueWidth = 5; // 5-wide issue for expanded uops
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let MicroOpBufferSize = 128; // Out-of-order with temporary unified issue buffer
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let LoadLatency = 4; // Optimistic load latency
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let MispredictPenalty = 14; // Fetch + Decode/Rename/Dispatch + Branch
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// Enable partial & runtime unrolling. The magic number is chosen based on
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// experiments and benchmarking data.
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let LoopMicroOpBufferSize = 16;
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let CompleteModel = 1;
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list<Predicate> UnsupportedFeatures = [HasSVE];
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}
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//===----------------------------------------------------------------------===//
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// Define each kind of processor resource and number available on Kryo.
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let SchedModel = KryoModel in {
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def KryoUnitXA : ProcResource<1>; // Type X(A) micro-ops
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def KryoUnitXB : ProcResource<1>; // Type X(B) micro-ops
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def KryoUnitYA : ProcResource<1>; // Type Y(A) micro-ops
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def KryoUnitYB : ProcResource<1>; // Type Y(B) micro-ops
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def KryoUnitX : ProcResGroup<[KryoUnitXA, // Type X micro-ops
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KryoUnitXB]>;
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def KryoUnitY : ProcResGroup<[KryoUnitYA, // Type Y micro-ops
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KryoUnitYB]>;
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def KryoUnitXY : ProcResGroup<[KryoUnitXA, // Type XY micro-ops
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KryoUnitXB,
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KryoUnitYA,
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KryoUnitYB]>;
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def KryoUnitLSA : ProcResource<1>; // Type LS(A) micro-ops
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def KryoUnitLSB : ProcResource<1>; // Type LS(B) micro-ops
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def KryoUnitLS : ProcResGroup<[KryoUnitLSA, // Type LS micro-ops
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KryoUnitLSB]>;
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}
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let SchedModel = KryoModel in {
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//===----------------------------------------------------------------------===//
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// Map the target-defined scheduler read/write resources and latency for
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// Kryo.
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def : WriteRes<WriteImm, [KryoUnitXY]> { let Latency = 1; }
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def : WriteRes<WriteI, [KryoUnitXY]> { let Latency = 1; }
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def : WriteRes<WriteISReg, [KryoUnitXY, KryoUnitXY]>
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{ let Latency = 2; let NumMicroOps = 2; }
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def : WriteRes<WriteIEReg, [KryoUnitXY, KryoUnitXY]>
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{ let Latency = 2; let NumMicroOps = 2; }
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def : WriteRes<WriteExtr, [KryoUnitXY, KryoUnitX]>
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{ let Latency = 2; let NumMicroOps = 2; }
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def : WriteRes<WriteIS, [KryoUnitXY]> { let Latency = 2; }
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def : WriteRes<WriteID32, [KryoUnitXA, KryoUnitY]>
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{ let Latency = 8; let NumMicroOps = 1; } // Fragent -1
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def : WriteRes<WriteID64, [KryoUnitXA, KryoUnitY]>
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{ let Latency = 8; let NumMicroOps = 1; } // Fragent -1
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def : WriteRes<WriteIM32, [KryoUnitX]> { let Latency = 5; }
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def : WriteRes<WriteIM64, [KryoUnitX]> { let Latency = 5; }
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def : WriteRes<WriteBr, [KryoUnitXY]> { let Latency = 1; }
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def : WriteRes<WriteBrReg, [KryoUnitXY]> { let Latency = 1; }
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def : WriteRes<WriteLD, [KryoUnitLS]> { let Latency = 4; }
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def : WriteRes<WriteST, [KryoUnitLS]> { let Latency = 4; }
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def : WriteRes<WriteSTP, [KryoUnitLS]> { let Latency = 4; }
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def : WriteRes<WriteAdr, [KryoUnitXY]> { let Latency = 6; }
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def : WriteRes<WriteLDIdx, [KryoUnitLS]> { let Latency = 4; }
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def : WriteRes<WriteSTIdx, [KryoUnitLS]> { let Latency = 4; }
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def : WriteRes<WriteF, [KryoUnitXY, KryoUnitXY]>
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{ let Latency = 3; let NumMicroOps = 2; }
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def : WriteRes<WriteFCmp, [KryoUnitXY]> { let Latency = 2; }
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def : WriteRes<WriteFCvt, [KryoUnitX]> { let Latency = 4; }
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def : WriteRes<WriteFCopy, [KryoUnitXY]> { let Latency = 6; }
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def : WriteRes<WriteFImm, [KryoUnitXY]> { let Latency = 6; }
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def : WriteRes<WriteFMul, [KryoUnitX, KryoUnitX]>
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{ let Latency = 6; let NumMicroOps = 2; }
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def : WriteRes<WriteFDiv, [KryoUnitXA, KryoUnitY]>
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{ let Latency = 12; let NumMicroOps = 2; } // Fragent -1 / NoRSV +1
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def : WriteRes<WriteV, [KryoUnitXY]> { let Latency = 6; }
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def : WriteRes<WriteVLD, [KryoUnitLS]> { let Latency = 4; }
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def : WriteRes<WriteVST, [KryoUnitLS]> { let Latency = 4; }
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def : WriteRes<WriteSys, []> { let Latency = 1; }
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def : WriteRes<WriteBarrier, []> { let Latency = 1; }
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def : WriteRes<WriteHint, []> { let Latency = 1; }
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def : WriteRes<WriteLDHi, []> { let Latency = 4; }
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def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
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// No forwarding logic is modelled yet.
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def : ReadAdvance<ReadI, 0>;
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def : ReadAdvance<ReadISReg, 0>;
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def : ReadAdvance<ReadIEReg, 0>;
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def : ReadAdvance<ReadIM, 0>;
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def : ReadAdvance<ReadIMA, 0>;
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def : ReadAdvance<ReadID, 0>;
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def : ReadAdvance<ReadExtrHi, 0>;
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def : ReadAdvance<ReadAdrBase, 0>;
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def : ReadAdvance<ReadVLD, 0>;
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//===----------------------------------------------------------------------===//
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// Specialize the coarse model by associating instruction groups with the
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// subtarget-defined types. As the modeled is refined, this will override most
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// of the above SchedWriteRes and SchedAlias mappings.
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// Miscellaneous
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// -----------------------------------------------------------------------------
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def : InstRW<[WriteI], (instrs COPY)>;
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// Detailed Refinedments
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// -----------------------------------------------------------------------------
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include "AArch64SchedKryoDetails.td"
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} // SchedModel = KryoModel
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