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llvm-mirror/test/CodeGen/Hexagon/fadd.ll
Sirish Pande 7fbfe4a1d6 Hexagon V5 FP Support.
llvm-svn: 156568
2012-05-10 20:20:25 +00:00

19 lines
546 B
LLVM

; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
; Check that we generate sp floating point add in V5.
; CHECK: r{{[0-9]+}} = sfadd(r{{[0-9]+}}, r{{[0-9]+}})
define i32 @main() nounwind {
entry:
%a = alloca float, align 4
%b = alloca float, align 4
%c = alloca float, align 4
store float 0x402ECCCCC0000000, float* %a, align 4
store float 0x4022333340000000, float* %b, align 4
%0 = load float* %a, align 4
%1 = load float* %b, align 4
%add = fadd float %0, %1
store float %add, float* %c, align 4
ret i32 0
}