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a515fb7c17
* Added R600_Reg64 class
* Added T#Index#.XY registers definition
* Added v2i32 register reads from parameter and global space
* Added f32 and i32 elements extraction from v2f32 and v2i32
* Added v2i32 -> v2f32 conversions
Tom Stellard:
- Mark vec2 operations as expand. The addition of a vec2 register
class made them all legal.
Patch by: Dmitry Cherkassov
Signed-off-by: Dmitry Cherkassov <dcherkassov@gmail.com>
llvm-svn: 187582
25 lines
952 B
LLVM
25 lines
952 B
LLVM
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
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; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI-CHECK %s
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; load a v2i32 value from the global address space.
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; EG-CHECK: @load_v2i32
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; EG-CHECK: VTX_READ_64 T{{[0-9]+}}.XY, T{{[0-9]+}}.X, 0
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; SI-CHECK: @load_v2i32
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; SI-CHECK: BUFFER_LOAD_DWORDX2 VGPR{{[0-9]+}}
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define void @load_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
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%a = load <2 x i32> addrspace(1) * %in
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store <2 x i32> %a, <2 x i32> addrspace(1)* %out
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ret void
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}
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; load a v4i32 value from the global address space.
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; EG-CHECK: @load_v4i32
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; EG-CHECK: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0
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; SI-CHECK: @load_v4i32
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; SI-CHECK: BUFFER_LOAD_DWORDX4 VGPR{{[0-9]+}}
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define void @load_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
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%a = load <4 x i32> addrspace(1) * %in
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store <4 x i32> %a, <4 x i32> addrspace(1)* %out
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ret void
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}
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