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4d570a3f0e
the feature set of v7a. This comes about if the user specifies something like -arch armv7 -mcpu=cortex-m3. We shouldn't be generating instructions such as uxtab in this case. rdar://11318438 llvm-svn: 155601
36 lines
807 B
LLVM
36 lines
807 B
LLVM
; RUN: llc < %s -march=thumb -mcpu=cortex-a8 | FileCheck %s --check-prefix=A8
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; RUN: llc < %s -march=thumb -mcpu=cortex-m3 | FileCheck %s --check-prefix=M3
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; rdar://11318438
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define zeroext i8 @test1(i32 %A.u) {
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; A8: test1
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; A8: uxtb r0, r0
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%B.u = trunc i32 %A.u to i8
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ret i8 %B.u
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}
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define zeroext i32 @test2(i32 %A.u, i32 %B.u) {
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; A8: test2
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; A8: uxtab r0, r0, r1
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; M3: test2
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; M3: uxtb r1, r1
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; M3-NOT: uxtab
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; M3: add r0, r1
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%C.u = trunc i32 %B.u to i8
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%D.u = zext i8 %C.u to i32
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%E.u = add i32 %A.u, %D.u
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ret i32 %E.u
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}
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define zeroext i32 @test3(i32 %A.u) {
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; A8: test3
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; A8: uxth.w r0, r0, ror #8
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%B.u = lshr i32 %A.u, 8
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%C.u = shl i32 %A.u, 24
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%D.u = or i32 %B.u, %C.u
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%E.u = trunc i32 %D.u to i16
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%F.u = zext i16 %E.u to i32
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ret i32 %F.u
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}
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