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8f9591eb21
The recently announced IBM z15 processor implements the architecture already supported as "arch13" in LLVM. This patch adds support for "z15" as an alternate architecture name for arch13. The patch also uses z15 in a number of places where we used arch13 as long as the official name was not yet announced. llvm-svn: 372435
77 lines
2.2 KiB
LLVM
77 lines
2.2 KiB
LLVM
; Test SELFHR.
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; See comments in asm-18.ll about testing high-word operations.
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;
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; RUN: llc < %s -verify-machineinstrs -mtriple=s390x-linux-gnu -mcpu=z15 \
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; RUN: -no-integrated-as | FileCheck %s
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define void @f1(i32 %limit) {
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; CHECK-LABEL: f1:
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; CHECK-DAG: stepa [[REG1:%r[0-5]]]
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; CHECK-DAG: stepb [[REG2:%r[0-5]]]
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; CHECK-DAG: clfi %r2, 42
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; CHECK: selfhrl [[REG3:%r[0-5]]], [[REG1]], [[REG2]]
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; CHECK: stepc [[REG3]]
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; CHECK: br %r14
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%a = call i32 asm sideeffect "stepa $0", "=h"()
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%b = call i32 asm sideeffect "stepb $0", "=h"()
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%cond = icmp ult i32 %limit, 42
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%res = select i1 %cond, i32 %a, i32 %b
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call void asm sideeffect "stepc $0", "h"(i32 %res)
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call void asm sideeffect "use $0", "h"(i32 %a)
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call void asm sideeffect "use $0", "h"(i32 %b)
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ret void
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}
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; Check that we also get SELFHR as a result of early if-conversion.
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define void @f2(i32 %limit) {
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; CHECK-LABEL: f2:
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; CHECK-DAG: stepa [[REG1:%r[0-5]]]
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; CHECK-DAG: stepb [[REG2:%r[0-5]]]
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; CHECK-DAG: clfi %r2, 41
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; CHECK: selfhrh [[REG3:%r[0-5]]], [[REG2]], [[REG1]]
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; CHECK: stepc [[REG3]]
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; CHECK: br %r14
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entry:
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%a = call i32 asm sideeffect "stepa $0", "=h"()
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%b = call i32 asm sideeffect "stepb $0", "=h"()
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%cond = icmp ult i32 %limit, 42
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br i1 %cond, label %if.then, label %return
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if.then:
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br label %return
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return:
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%res = phi i32 [ %a, %if.then ], [ %b, %entry ]
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call void asm sideeffect "stepc $0", "h"(i32 %res)
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call void asm sideeffect "use $0", "h"(i32 %a)
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call void asm sideeffect "use $0", "h"(i32 %b)
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ret void
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}
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; Check that inverting the condition works as well.
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define void @f3(i32 %limit) {
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; CHECK-LABEL: f3:
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; CHECK-DAG: stepa [[REG1:%r[0-5]]]
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; CHECK-DAG: stepb [[REG2:%r[0-5]]]
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; CHECK-DAG: clfi %r2, 41
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; CHECK: selfhrh [[REG3:%r[0-5]]], [[REG1]], [[REG2]]
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; CHECK: stepc [[REG3]]
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; CHECK: br %r14
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entry:
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%a = call i32 asm sideeffect "stepa $0", "=h"()
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%b = call i32 asm sideeffect "stepb $0", "=h"()
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%cond = icmp ult i32 %limit, 42
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br i1 %cond, label %if.then, label %return
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if.then:
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br label %return
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return:
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%res = phi i32 [ %b, %if.then ], [ %a, %entry ]
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call void asm sideeffect "stepc $0", "h"(i32 %res)
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call void asm sideeffect "use $0", "h"(i32 %a)
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call void asm sideeffect "use $0", "h"(i32 %b)
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ret void
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}
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