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5f15092063
This patch series adds support for the IBM z14 processor. This part includes: - Basic support for the new processor and its features. - Support for new instructions (except vector 32-bit float and 128-bit float). - CodeGen for new instructions, including new LLVM intrinsics. - Scheduler description for the new processor. - Detection of z14 as host processor. Support for the new 32-bit vector float and 128-bit vector float instructions is provided by separate patches. llvm-svn: 308194
96 lines
2.4 KiB
LLVM
96 lines
2.4 KiB
LLVM
; Test subtractions of a sign-extended i16 from an i64 on z14.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s
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declare i64 @foo()
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; Check SGH with no displacement.
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define i64 @f1(i64 %a, i16 *%src) {
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; CHECK-LABEL: f1:
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; CHECK: sgh %r2, 0(%r3)
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; CHECK: br %r14
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%b = load i16, i16 *%src
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%bext = sext i16 %b to i64
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%sub = sub i64 %a, %bext
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ret i64 %sub
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}
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; Check the high end of the aligned SGH range.
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define i64 @f2(i64 %a, i16 *%src) {
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; CHECK-LABEL: f2:
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; CHECK: sgh %r2, 524286(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i16, i16 *%src, i64 262143
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%b = load i16, i16 *%ptr
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%bext = sext i16 %b to i64
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%sub = sub i64 %a, %bext
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ret i64 %sub
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}
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; Check the next word up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f3(i64 %a, i16 *%src) {
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; CHECK-LABEL: f3:
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; CHECK: agfi %r3, 524288
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; CHECK: sgh %r2, 0(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i16, i16 *%src, i64 262144
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%b = load i16, i16 *%ptr
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%bext = sext i16 %b to i64
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%sub = sub i64 %a, %bext
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ret i64 %sub
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}
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; Check the high end of the negative aligned SGH range.
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define i64 @f4(i64 %a, i16 *%src) {
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; CHECK-LABEL: f4:
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; CHECK: sgh %r2, -2(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i16, i16 *%src, i64 -1
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%b = load i16, i16 *%ptr
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%bext = sext i16 %b to i64
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%sub = sub i64 %a, %bext
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ret i64 %sub
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}
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; Check the low end of the SGH range.
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define i64 @f5(i64 %a, i16 *%src) {
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; CHECK-LABEL: f5:
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; CHECK: sgh %r2, -524288(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i16, i16 *%src, i64 -262144
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%b = load i16, i16 *%ptr
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%bext = sext i16 %b to i64
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%sub = sub i64 %a, %bext
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ret i64 %sub
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}
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; Check the next word down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f6(i64 %a, i16 *%src) {
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; CHECK-LABEL: f6:
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; CHECK: agfi %r3, -524290
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; CHECK: sgh %r2, 0(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i16, i16 *%src, i64 -262145
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%b = load i16, i16 *%ptr
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%bext = sext i16 %b to i64
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%sub = sub i64 %a, %bext
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ret i64 %sub
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}
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; Check that SGH allows an index.
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define i64 @f7(i64 %a, i64 %src, i64 %index) {
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; CHECK-LABEL: f7:
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; CHECK: sgh %r2, 524284({{%r4,%r3|%r3,%r4}})
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 524284
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%ptr = inttoptr i64 %add2 to i16 *
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%b = load i16, i16 *%ptr
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%bext = sext i16 %b to i64
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%sub = sub i64 %a, %bext
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ret i64 %sub
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}
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