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90d0031df7
On SystemZ, a ZERO_EXTEND of an i1 vector handled by WidenVecRes_Convert() always ended up being scalarized, because the type action of the input is promotion which was previously an unhandled case in this method. This fixes https://bugs.llvm.org/show_bug.cgi?id=47132. Differential Revision: https://reviews.llvm.org/D86268 Patch by Eli Friedman. Review: Ulrich Weigand
111 lines
2.8 KiB
LLVM
111 lines
2.8 KiB
LLVM
; Test that vector zexts are done efficently also in case of fewer elements
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; than allowed, e.g. <2 x i32>.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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define <2 x i16> @fun1(<2 x i8> %val1) {
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; CHECK-LABEL: fun1:
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; CHECK: vuplhb %v24, %v24
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; CHECK-NEXT: br %r14
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%z = zext <2 x i8> %val1 to <2 x i16>
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ret <2 x i16> %z
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}
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define <2 x i32> @fun2(<2 x i8> %val1) {
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; CHECK-LABEL: fun2:
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; CHECK: larl %r1, .LCPI1_0
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; CHECK-NEXT: vl %v0, 0(%r1), 3
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; CHECK-NEXT: vperm %v24, %v0, %v24, %v0
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; CHECK-NEXT: br %r14
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%z = zext <2 x i8> %val1 to <2 x i32>
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ret <2 x i32> %z
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}
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define <2 x i64> @fun3(<2 x i8> %val1) {
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; CHECK-LABEL: fun3:
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; CHECK: larl %r1, .LCPI2_0
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; CHECK-NEXT: vl %v0, 0(%r1), 3
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; CHECK-NEXT: vperm %v24, %v0, %v24, %v0
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; CHECK-NEXT: br %r14
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%z = zext <2 x i8> %val1 to <2 x i64>
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ret <2 x i64> %z
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}
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define <2 x i32> @fun4(<2 x i16> %val1) {
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; CHECK-LABEL: fun4:
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; CHECK: vuplhh %v24, %v24
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; CHECK-NEXT: br %r14
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%z = zext <2 x i16> %val1 to <2 x i32>
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ret <2 x i32> %z
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}
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define <2 x i64> @fun5(<2 x i16> %val1) {
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; CHECK-LABEL: fun5:
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; CHECK: larl %r1, .LCPI4_0
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; CHECK-NEXT: vl %v0, 0(%r1), 3
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; CHECK-NEXT: vperm %v24, %v0, %v24, %v0
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; CHECK-NEXT: br %r14
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%z = zext <2 x i16> %val1 to <2 x i64>
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ret <2 x i64> %z
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}
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define <2 x i64> @fun6(<2 x i32> %val1) {
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; CHECK-LABEL: fun6:
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; CHECK: vuplhf %v24, %v24
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; CHECK-NEXT: br %r14
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%z = zext <2 x i32> %val1 to <2 x i64>
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ret <2 x i64> %z
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}
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define <4 x i16> @fun7(<4 x i8> %val1) {
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; CHECK-LABEL: fun7:
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; CHECK: vuplhb %v24, %v24
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; CHECK-NEXT: br %r14
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%z = zext <4 x i8> %val1 to <4 x i16>
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ret <4 x i16> %z
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}
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define <4 x i32> @fun8(<4 x i8> %val1) {
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; CHECK-LABEL: fun8:
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; CHECK: larl %r1, .LCPI7_0
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; CHECK-NEXT: vl %v0, 0(%r1), 3
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; CHECK-NEXT: vperm %v24, %v0, %v24, %v0
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; CHECK-NEXT: br %r14
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%z = zext <4 x i8> %val1 to <4 x i32>
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ret <4 x i32> %z
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}
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define <4 x i32> @fun9(<4 x i16> %val1) {
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; CHECK-LABEL: fun9:
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; CHECK: vuplhh %v24, %v24
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; CHECK-NEXT: br %r14
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%z = zext <4 x i16> %val1 to <4 x i32>
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ret <4 x i32> %z
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}
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define <8 x i16> @fun10(<8 x i8> %val1) {
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; CHECK-LABEL: fun10:
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; CHECK: vuplhb %v24, %v24
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; CHECK-NEXT: br %r14
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%z = zext <8 x i8> %val1 to <8 x i16>
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ret <8 x i16> %z
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}
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define <2 x i32> @fun11(<2 x i64> %Arg1, <2 x i64> %Arg2) {
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; CHECK-LABEL: fun11:
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; CHECK: vgbm %v0, 0
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; CHECK-NEXT: vceqg %v1, %v24, %v0
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; CHECK-NEXT: vceqg %v0, %v26, %v0
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; CHECK-NEXT: vo %v0, %v1, %v0
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; CHECK-NEXT: vrepig %v1, 1
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; CHECK-NEXT: vn %v0, %v0, %v1
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; CHECK-NEXT: vpkg %v24, %v0, %v0
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; CHECK-NEXT: br %r14
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%i3 = icmp eq <2 x i64> %Arg1, zeroinitializer
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%i5 = icmp eq <2 x i64> %Arg2, zeroinitializer
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%i6 = or <2 x i1> %i3, %i5
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%i7 = zext <2 x i1> %i6 to <2 x i32>
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ret <2 x i32> %i7
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}
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