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c46fc6adbe
At the moment we use Global ISel by default at -O0, however it is currently not capable of dealing with scalable vectors for two reasons: 1. The register banks know nothing about SVE registers. 2. The LLT (Low Level Type) class knows nothing about scalable vectors. For now, the easiest way to avoid users hitting issues when using the SVE ACLE is to fall back on normal DAG ISel when encountering instructions that operate on scalable vector types. I've added a couple of RUN lines to existing SVE tests to ensure we can compile at -O0. I've also added some new tests to CodeGen/AArch64/GlobalISel/arm64-fallback.ll that demonstrate we correctly fallback to DAG ISel at -O0 when lowering formal arguments or translating instructions that involve scalable vector types. Differential Revision: https://reviews.llvm.org/D81557 |
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| AArch64 | ||
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| ARC | ||
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| AVR | ||
| BPF | ||
| Generic | ||
| Hexagon | ||
| Inputs | ||
| Lanai | ||
| Mips | ||
| MIR | ||
| MSP430 | ||
| NVPTX | ||
| PowerPC | ||
| RISCV | ||
| SPARC | ||
| SystemZ | ||
| Thumb | ||
| Thumb2 | ||
| VE | ||
| WebAssembly | ||
| WinCFGuard | ||
| WinEH | ||
| X86 | ||
| XCore | ||