mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-23 13:02:52 +02:00
d5cead992a
This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
915 lines
21 KiB
YAML
915 lines
21 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
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--- |
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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define void @add_s32_gpr() { ret void }
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define void @add_s64_gpr() { ret void }
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define void @add_imm_s32_gpr() { ret void }
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define void @add_imm_s64_gpr() { ret void }
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define void @add_imm_s32_gpr_bb() { ret void }
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define void @sub_s32_gpr() { ret void }
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define void @sub_s64_gpr() { ret void }
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define void @or_s32_gpr() { ret void }
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define void @or_s64_gpr() { ret void }
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define void @or_v2s32_fpr() { ret void }
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define void @and_s32_gpr() { ret void }
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define void @and_s64_gpr() { ret void }
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define void @shl_s32_gpr() { ret void }
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define void @shl_s64_gpr() { ret void }
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define void @lshr_s32_gpr() { ret void }
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define void @lshr_s64_gpr() { ret void }
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define void @ashr_s32_gpr() { ret void }
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define void @ashr_s64_gpr() { ret void }
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define void @mul_s32_gpr() { ret void }
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define void @mul_s64_gpr() { ret void }
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define void @mulh_s64_gpr() { ret void }
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define void @sdiv_s32_gpr() { ret void }
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define void @sdiv_s64_gpr() { ret void }
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define void @udiv_s32_gpr() { ret void }
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define void @udiv_s64_gpr() { ret void }
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define void @fadd_s32_fpr() { ret void }
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define void @fadd_s64_fpr() { ret void }
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define void @fsub_s32_fpr() { ret void }
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define void @fsub_s64_fpr() { ret void }
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define void @fmul_s32_fpr() { ret void }
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define void @fmul_s64_fpr() { ret void }
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define void @fdiv_s32_fpr() { ret void }
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define void @fdiv_s64_fpr() { ret void }
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...
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---
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# Check that we select a 32-bit GPR G_ADD into ADDWrr on GPR32.
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# Also check that we constrain the register class of the COPY to GPR32.
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name: add_s32_gpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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body: |
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bb.0:
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liveins: %w0, %w1
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; CHECK-LABEL: name: add_s32_gpr
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
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; CHECK: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]]
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; CHECK: %w0 = COPY [[ADDWrr]]
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%0(s32) = COPY %w0
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%1(s32) = COPY %w1
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%2(s32) = G_ADD %0, %1
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%w0 = COPY %2(s32)
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...
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---
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# Same as add_s32_gpr, for 64-bit operations.
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name: add_s64_gpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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body: |
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bb.0:
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liveins: %x0, %x1
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; CHECK-LABEL: name: add_s64_gpr
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
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; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
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; CHECK: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[COPY1]]
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; CHECK: %x0 = COPY [[ADDXrr]]
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%0(s64) = COPY %x0
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%1(s64) = COPY %x1
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%2(s64) = G_ADD %0, %1
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%x0 = COPY %2(s64)
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...
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---
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name: add_imm_s32_gpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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body: |
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bb.0:
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liveins: %w0, %w1
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; CHECK-LABEL: name: add_imm_s32_gpr
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; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY %w0
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; CHECK: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY]], 1, 0
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; CHECK: %w0 = COPY [[ADDWri]]
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%0(s32) = COPY %w0
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%1(s32) = G_CONSTANT i32 1
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%2(s32) = G_ADD %0, %1
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%w0 = COPY %2(s32)
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...
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---
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name: add_imm_s64_gpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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body: |
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bb.0:
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liveins: %x0, %w1
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; CHECK-LABEL: name: add_imm_s64_gpr
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
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; CHECK: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY]], 1, 0
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; CHECK: %x0 = COPY [[ADDXri]]
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%0(s64) = COPY %x0
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%1(s64) = G_CONSTANT i32 1
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%2(s64) = G_ADD %0, %1
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%x0 = COPY %2(s64)
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...
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---
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name: add_imm_s32_gpr_bb
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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body: |
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; CHECK-LABEL: name: add_imm_s32_gpr_bb
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY %w0
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; CHECK: B %bb.1
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; CHECK: bb.1:
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; CHECK: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY]], 1, 0
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; CHECK: %w0 = COPY [[ADDWri]]
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bb.0:
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liveins: %w0, %w1
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successors: %bb.1
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%0(s32) = COPY %w0
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%1(s32) = G_CONSTANT i32 1
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G_BR %bb.1
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bb.1:
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%2(s32) = G_ADD %0, %1
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%w0 = COPY %2(s32)
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...
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---
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# Same as add_s32_gpr, for G_SUB operations.
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name: sub_s32_gpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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body: |
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bb.0:
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liveins: %w0, %w1
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; CHECK-LABEL: name: sub_s32_gpr
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
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; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY]], [[COPY1]], implicit-def %nzcv
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; CHECK: %w0 = COPY [[SUBSWrr]]
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%0(s32) = COPY %w0
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%1(s32) = COPY %w1
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%2(s32) = G_SUB %0, %1
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%w0 = COPY %2(s32)
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...
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---
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# Same as add_s64_gpr, for G_SUB operations.
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name: sub_s64_gpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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body: |
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bb.0:
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liveins: %x0, %x1
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; CHECK-LABEL: name: sub_s64_gpr
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
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; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
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; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[COPY1]], implicit-def %nzcv
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; CHECK: %x0 = COPY [[SUBSXrr]]
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%0(s64) = COPY %x0
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%1(s64) = COPY %x1
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%2(s64) = G_SUB %0, %1
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%x0 = COPY %2(s64)
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...
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---
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# Same as add_s32_gpr, for G_OR operations.
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name: or_s32_gpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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body: |
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bb.0:
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liveins: %w0, %w1
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; CHECK-LABEL: name: or_s32_gpr
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
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; CHECK: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[COPY]], [[COPY1]]
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; CHECK: %w0 = COPY [[ORRWrr]]
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%0(s32) = COPY %w0
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%1(s32) = COPY %w1
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%2(s32) = G_OR %0, %1
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%w0 = COPY %2(s32)
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...
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---
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# Same as add_s64_gpr, for G_OR operations.
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name: or_s64_gpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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body: |
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bb.0:
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liveins: %x0, %x1
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; CHECK-LABEL: name: or_s64_gpr
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
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; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
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; CHECK: [[ORRXrr:%[0-9]+]]:gpr64 = ORRXrr [[COPY]], [[COPY1]]
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; CHECK: %x0 = COPY [[ORRXrr]]
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%0(s64) = COPY %x0
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%1(s64) = COPY %x1
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%2(s64) = G_OR %0, %1
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%x0 = COPY %2(s64)
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...
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---
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# 64-bit G_OR on vector registers.
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name: or_v2s32_fpr
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legalized: true
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regBankSelected: true
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#
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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- { id: 2, class: fpr }
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# The actual OR does not matter as long as it is operating
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# on 64-bit width vector.
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body: |
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bb.0:
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liveins: %d0, %d1
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; CHECK-LABEL: name: or_v2s32_fpr
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
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; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY %d1
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; CHECK: [[ORRv8i8_:%[0-9]+]]:fpr64 = ORRv8i8 [[COPY]], [[COPY1]]
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; CHECK: %d0 = COPY [[ORRv8i8_]]
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%0(<2 x s32>) = COPY %d0
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%1(<2 x s32>) = COPY %d1
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%2(<2 x s32>) = G_OR %0, %1
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%d0 = COPY %2(<2 x s32>)
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...
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---
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# Same as add_s32_gpr, for G_AND operations.
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name: and_s32_gpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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body: |
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bb.0:
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liveins: %w0, %w1
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; CHECK-LABEL: name: and_s32_gpr
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
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; CHECK: [[ANDWrr:%[0-9]+]]:gpr32 = ANDWrr [[COPY]], [[COPY1]]
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; CHECK: %w0 = COPY [[ANDWrr]]
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%0(s32) = COPY %w0
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%1(s32) = COPY %w1
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%2(s32) = G_AND %0, %1
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%w0 = COPY %2(s32)
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...
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---
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# Same as add_s64_gpr, for G_AND operations.
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name: and_s64_gpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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body: |
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bb.0:
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liveins: %x0, %x1
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; CHECK-LABEL: name: and_s64_gpr
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
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; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
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; CHECK: [[ANDXrr:%[0-9]+]]:gpr64 = ANDXrr [[COPY]], [[COPY1]]
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; CHECK: %x0 = COPY [[ANDXrr]]
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%0(s64) = COPY %x0
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%1(s64) = COPY %x1
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%2(s64) = G_AND %0, %1
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%x0 = COPY %2(s64)
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...
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---
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# Same as add_s32_gpr, for G_SHL operations.
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name: shl_s32_gpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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body: |
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bb.0:
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liveins: %w0, %w1
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; CHECK-LABEL: name: shl_s32_gpr
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
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; CHECK: [[LSLVWr:%[0-9]+]]:gpr32 = LSLVWr [[COPY]], [[COPY1]]
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; CHECK: %w0 = COPY [[LSLVWr]]
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%0(s32) = COPY %w0
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%1(s32) = COPY %w1
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%2(s32) = G_SHL %0, %1
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%w0 = COPY %2(s32)
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...
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---
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# Same as add_s64_gpr, for G_SHL operations.
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name: shl_s64_gpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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body: |
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bb.0:
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liveins: %x0, %x1
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; CHECK-LABEL: name: shl_s64_gpr
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
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; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
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; CHECK: [[LSLVXr:%[0-9]+]]:gpr64 = LSLVXr [[COPY]], [[COPY1]]
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; CHECK: %x0 = COPY [[LSLVXr]]
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%0(s64) = COPY %x0
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%1(s64) = COPY %x1
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%2(s64) = G_SHL %0, %1
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%x0 = COPY %2(s64)
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...
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---
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# Same as add_s32_gpr, for G_LSHR operations.
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name: lshr_s32_gpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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body: |
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bb.0:
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liveins: %w0, %w1
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; CHECK-LABEL: name: lshr_s32_gpr
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
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; CHECK: [[LSRVWr:%[0-9]+]]:gpr32 = LSRVWr [[COPY]], [[COPY1]]
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; CHECK: %w0 = COPY [[LSRVWr]]
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%0(s32) = COPY %w0
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%1(s32) = COPY %w1
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%2(s32) = G_LSHR %0, %1
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%w0 = COPY %2(s32)
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...
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---
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# Same as add_s64_gpr, for G_LSHR operations.
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name: lshr_s64_gpr
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legalized: true
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regBankSelected: true
|
|
|
|
registers:
|
|
- { id: 0, class: gpr }
|
|
- { id: 1, class: gpr }
|
|
- { id: 2, class: gpr }
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: %x0, %x1
|
|
|
|
; CHECK-LABEL: name: lshr_s64_gpr
|
|
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
|
|
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
|
|
; CHECK: [[LSRVXr:%[0-9]+]]:gpr64 = LSRVXr [[COPY]], [[COPY1]]
|
|
; CHECK: %x0 = COPY [[LSRVXr]]
|
|
%0(s64) = COPY %x0
|
|
%1(s64) = COPY %x1
|
|
%2(s64) = G_LSHR %0, %1
|
|
%x0 = COPY %2(s64)
|
|
...
|
|
|
|
---
|
|
# Same as add_s32_gpr, for G_ASHR operations.
|
|
name: ashr_s32_gpr
|
|
legalized: true
|
|
regBankSelected: true
|
|
|
|
registers:
|
|
- { id: 0, class: gpr }
|
|
- { id: 1, class: gpr }
|
|
- { id: 2, class: gpr }
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: %w0, %w1
|
|
|
|
; CHECK-LABEL: name: ashr_s32_gpr
|
|
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
|
|
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
|
|
; CHECK: [[ASRVWr:%[0-9]+]]:gpr32 = ASRVWr [[COPY]], [[COPY1]]
|
|
; CHECK: %w0 = COPY [[ASRVWr]]
|
|
%0(s32) = COPY %w0
|
|
%1(s32) = COPY %w1
|
|
%2(s32) = G_ASHR %0, %1
|
|
%w0 = COPY %2(s32)
|
|
...
|
|
|
|
---
|
|
# Same as add_s64_gpr, for G_ASHR operations.
|
|
name: ashr_s64_gpr
|
|
legalized: true
|
|
regBankSelected: true
|
|
|
|
registers:
|
|
- { id: 0, class: gpr }
|
|
- { id: 1, class: gpr }
|
|
- { id: 2, class: gpr }
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: %x0, %x1
|
|
|
|
; CHECK-LABEL: name: ashr_s64_gpr
|
|
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
|
|
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
|
|
; CHECK: [[ASRVXr:%[0-9]+]]:gpr64 = ASRVXr [[COPY]], [[COPY1]]
|
|
; CHECK: %x0 = COPY [[ASRVXr]]
|
|
%0(s64) = COPY %x0
|
|
%1(s64) = COPY %x1
|
|
%2(s64) = G_ASHR %0, %1
|
|
%x0 = COPY %2(s64)
|
|
...
|
|
|
|
---
|
|
# Check that we select s32 GPR G_MUL. This is trickier than other binops because
|
|
# there is only MADDWrrr, and we have to use the WZR physreg.
|
|
name: mul_s32_gpr
|
|
legalized: true
|
|
regBankSelected: true
|
|
|
|
registers:
|
|
- { id: 0, class: gpr }
|
|
- { id: 1, class: gpr }
|
|
- { id: 2, class: gpr }
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: %w0, %w1
|
|
|
|
; CHECK-LABEL: name: mul_s32_gpr
|
|
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
|
|
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
|
|
; CHECK: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY]], [[COPY1]], %wzr
|
|
; CHECK: %w0 = COPY [[MADDWrrr]]
|
|
%0(s32) = COPY %w0
|
|
%1(s32) = COPY %w1
|
|
%2(s32) = G_MUL %0, %1
|
|
%w0 = COPY %2(s32)
|
|
...
|
|
|
|
---
|
|
# Same as mul_s32_gpr for the s64 type.
|
|
name: mul_s64_gpr
|
|
legalized: true
|
|
regBankSelected: true
|
|
|
|
registers:
|
|
- { id: 0, class: gpr }
|
|
- { id: 1, class: gpr }
|
|
- { id: 2, class: gpr }
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: %x0, %x1
|
|
|
|
; CHECK-LABEL: name: mul_s64_gpr
|
|
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
|
|
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
|
|
; CHECK: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[COPY]], [[COPY1]], %xzr
|
|
; CHECK: %x0 = COPY [[MADDXrrr]]
|
|
%0(s64) = COPY %x0
|
|
%1(s64) = COPY %x1
|
|
%2(s64) = G_MUL %0, %1
|
|
%x0 = COPY %2(s64)
|
|
...
|
|
|
|
---
|
|
# Same as mul_s32_gpr for the s64 type.
|
|
name: mulh_s64_gpr
|
|
legalized: true
|
|
regBankSelected: true
|
|
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: %x0, %x1
|
|
|
|
; CHECK-LABEL: name: mulh_s64_gpr
|
|
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
|
|
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
|
|
; CHECK: [[SMULHrr:%[0-9]+]]:gpr64 = SMULHrr [[COPY]], [[COPY1]]
|
|
; CHECK: [[UMULHrr:%[0-9]+]]:gpr64 = UMULHrr [[COPY]], [[COPY1]]
|
|
; CHECK: %x0 = COPY [[SMULHrr]]
|
|
; CHECK: %x0 = COPY [[UMULHrr]]
|
|
%0:gpr(s64) = COPY %x0
|
|
%1:gpr(s64) = COPY %x1
|
|
%2:gpr(s64) = G_SMULH %0, %1
|
|
%3:gpr(s64) = G_UMULH %0, %1
|
|
%x0 = COPY %2(s64)
|
|
%x0 = COPY %3(s64)
|
|
...
|
|
|
|
---
|
|
# Same as add_s32_gpr, for G_SDIV operations.
|
|
name: sdiv_s32_gpr
|
|
legalized: true
|
|
regBankSelected: true
|
|
|
|
registers:
|
|
- { id: 0, class: gpr }
|
|
- { id: 1, class: gpr }
|
|
- { id: 2, class: gpr }
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: %w0, %w1
|
|
|
|
; CHECK-LABEL: name: sdiv_s32_gpr
|
|
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
|
|
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
|
|
; CHECK: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[COPY]], [[COPY1]]
|
|
; CHECK: %w0 = COPY [[SDIVWr]]
|
|
%0(s32) = COPY %w0
|
|
%1(s32) = COPY %w1
|
|
%2(s32) = G_SDIV %0, %1
|
|
%w0 = COPY %2(s32)
|
|
...
|
|
|
|
---
|
|
# Same as add_s64_gpr, for G_SDIV operations.
|
|
name: sdiv_s64_gpr
|
|
legalized: true
|
|
regBankSelected: true
|
|
|
|
registers:
|
|
- { id: 0, class: gpr }
|
|
- { id: 1, class: gpr }
|
|
- { id: 2, class: gpr }
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: %x0, %x1
|
|
|
|
; CHECK-LABEL: name: sdiv_s64_gpr
|
|
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
|
|
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
|
|
; CHECK: [[SDIVXr:%[0-9]+]]:gpr64 = SDIVXr [[COPY]], [[COPY1]]
|
|
; CHECK: %x0 = COPY [[SDIVXr]]
|
|
%0(s64) = COPY %x0
|
|
%1(s64) = COPY %x1
|
|
%2(s64) = G_SDIV %0, %1
|
|
%x0 = COPY %2(s64)
|
|
...
|
|
|
|
---
|
|
# Same as add_s32_gpr, for G_UDIV operations.
|
|
name: udiv_s32_gpr
|
|
legalized: true
|
|
regBankSelected: true
|
|
|
|
registers:
|
|
- { id: 0, class: gpr }
|
|
- { id: 1, class: gpr }
|
|
- { id: 2, class: gpr }
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: %w0, %w1
|
|
|
|
; CHECK-LABEL: name: udiv_s32_gpr
|
|
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
|
|
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
|
|
; CHECK: [[UDIVWr:%[0-9]+]]:gpr32 = UDIVWr [[COPY]], [[COPY1]]
|
|
; CHECK: %w0 = COPY [[UDIVWr]]
|
|
%0(s32) = COPY %w0
|
|
%1(s32) = COPY %w1
|
|
%2(s32) = G_UDIV %0, %1
|
|
%w0 = COPY %2(s32)
|
|
...
|
|
|
|
---
|
|
# Same as add_s64_gpr, for G_UDIV operations.
|
|
name: udiv_s64_gpr
|
|
legalized: true
|
|
regBankSelected: true
|
|
|
|
registers:
|
|
- { id: 0, class: gpr }
|
|
- { id: 1, class: gpr }
|
|
- { id: 2, class: gpr }
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: %x0, %x1
|
|
|
|
; CHECK-LABEL: name: udiv_s64_gpr
|
|
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
|
|
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
|
|
; CHECK: [[UDIVXr:%[0-9]+]]:gpr64 = UDIVXr [[COPY]], [[COPY1]]
|
|
; CHECK: %x0 = COPY [[UDIVXr]]
|
|
%0(s64) = COPY %x0
|
|
%1(s64) = COPY %x1
|
|
%2(s64) = G_UDIV %0, %1
|
|
%x0 = COPY %2(s64)
|
|
...
|
|
|
|
---
|
|
# Check that we select a s32 FPR G_FADD into FADDSrr.
|
|
name: fadd_s32_fpr
|
|
legalized: true
|
|
regBankSelected: true
|
|
|
|
registers:
|
|
- { id: 0, class: fpr }
|
|
- { id: 1, class: fpr }
|
|
- { id: 2, class: fpr }
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: %s0, %s1
|
|
|
|
; CHECK-LABEL: name: fadd_s32_fpr
|
|
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
|
|
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY %s1
|
|
; CHECK: [[FADDSrr:%[0-9]+]]:fpr32 = FADDSrr [[COPY]], [[COPY1]]
|
|
; CHECK: %s0 = COPY [[FADDSrr]]
|
|
%0(s32) = COPY %s0
|
|
%1(s32) = COPY %s1
|
|
%2(s32) = G_FADD %0, %1
|
|
%s0 = COPY %2(s32)
|
|
...
|
|
|
|
---
|
|
name: fadd_s64_fpr
|
|
legalized: true
|
|
regBankSelected: true
|
|
|
|
registers:
|
|
- { id: 0, class: fpr }
|
|
- { id: 1, class: fpr }
|
|
- { id: 2, class: fpr }
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: %d0, %d1
|
|
|
|
; CHECK-LABEL: name: fadd_s64_fpr
|
|
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
|
|
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY %d1
|
|
; CHECK: [[FADDDrr:%[0-9]+]]:fpr64 = FADDDrr [[COPY]], [[COPY1]]
|
|
; CHECK: %d0 = COPY [[FADDDrr]]
|
|
%0(s64) = COPY %d0
|
|
%1(s64) = COPY %d1
|
|
%2(s64) = G_FADD %0, %1
|
|
%d0 = COPY %2(s64)
|
|
...
|
|
|
|
---
|
|
name: fsub_s32_fpr
|
|
legalized: true
|
|
regBankSelected: true
|
|
|
|
registers:
|
|
- { id: 0, class: fpr }
|
|
- { id: 1, class: fpr }
|
|
- { id: 2, class: fpr }
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: %s0, %s1
|
|
|
|
; CHECK-LABEL: name: fsub_s32_fpr
|
|
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
|
|
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY %s1
|
|
; CHECK: [[FSUBSrr:%[0-9]+]]:fpr32 = FSUBSrr [[COPY]], [[COPY1]]
|
|
; CHECK: %s0 = COPY [[FSUBSrr]]
|
|
%0(s32) = COPY %s0
|
|
%1(s32) = COPY %s1
|
|
%2(s32) = G_FSUB %0, %1
|
|
%s0 = COPY %2(s32)
|
|
...
|
|
|
|
---
|
|
name: fsub_s64_fpr
|
|
legalized: true
|
|
regBankSelected: true
|
|
|
|
registers:
|
|
- { id: 0, class: fpr }
|
|
- { id: 1, class: fpr }
|
|
- { id: 2, class: fpr }
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: %d0, %d1
|
|
|
|
; CHECK-LABEL: name: fsub_s64_fpr
|
|
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
|
|
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY %d1
|
|
; CHECK: [[FSUBDrr:%[0-9]+]]:fpr64 = FSUBDrr [[COPY]], [[COPY1]]
|
|
; CHECK: %d0 = COPY [[FSUBDrr]]
|
|
%0(s64) = COPY %d0
|
|
%1(s64) = COPY %d1
|
|
%2(s64) = G_FSUB %0, %1
|
|
%d0 = COPY %2(s64)
|
|
...
|
|
|
|
---
|
|
name: fmul_s32_fpr
|
|
legalized: true
|
|
regBankSelected: true
|
|
|
|
registers:
|
|
- { id: 0, class: fpr }
|
|
- { id: 1, class: fpr }
|
|
- { id: 2, class: fpr }
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: %s0, %s1
|
|
|
|
; CHECK-LABEL: name: fmul_s32_fpr
|
|
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
|
|
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY %s1
|
|
; CHECK: [[FMULSrr:%[0-9]+]]:fpr32 = FMULSrr [[COPY]], [[COPY1]]
|
|
; CHECK: %s0 = COPY [[FMULSrr]]
|
|
%0(s32) = COPY %s0
|
|
%1(s32) = COPY %s1
|
|
%2(s32) = G_FMUL %0, %1
|
|
%s0 = COPY %2(s32)
|
|
...
|
|
|
|
---
|
|
name: fmul_s64_fpr
|
|
legalized: true
|
|
regBankSelected: true
|
|
|
|
registers:
|
|
- { id: 0, class: fpr }
|
|
- { id: 1, class: fpr }
|
|
- { id: 2, class: fpr }
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: %d0, %d1
|
|
|
|
; CHECK-LABEL: name: fmul_s64_fpr
|
|
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
|
|
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY %d1
|
|
; CHECK: [[FMULDrr:%[0-9]+]]:fpr64 = FMULDrr [[COPY]], [[COPY1]]
|
|
; CHECK: %d0 = COPY [[FMULDrr]]
|
|
%0(s64) = COPY %d0
|
|
%1(s64) = COPY %d1
|
|
%2(s64) = G_FMUL %0, %1
|
|
%d0 = COPY %2(s64)
|
|
...
|
|
|
|
---
|
|
name: fdiv_s32_fpr
|
|
legalized: true
|
|
regBankSelected: true
|
|
|
|
registers:
|
|
- { id: 0, class: fpr }
|
|
- { id: 1, class: fpr }
|
|
- { id: 2, class: fpr }
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: %s0, %s1
|
|
|
|
; CHECK-LABEL: name: fdiv_s32_fpr
|
|
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
|
|
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY %s1
|
|
; CHECK: [[FDIVSrr:%[0-9]+]]:fpr32 = FDIVSrr [[COPY]], [[COPY1]]
|
|
; CHECK: %s0 = COPY [[FDIVSrr]]
|
|
%0(s32) = COPY %s0
|
|
%1(s32) = COPY %s1
|
|
%2(s32) = G_FDIV %0, %1
|
|
%s0 = COPY %2(s32)
|
|
...
|
|
|
|
---
|
|
name: fdiv_s64_fpr
|
|
legalized: true
|
|
regBankSelected: true
|
|
|
|
registers:
|
|
- { id: 0, class: fpr }
|
|
- { id: 1, class: fpr }
|
|
- { id: 2, class: fpr }
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: %d0, %d1
|
|
|
|
; CHECK-LABEL: name: fdiv_s64_fpr
|
|
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
|
|
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY %d1
|
|
; CHECK: [[FDIVDrr:%[0-9]+]]:fpr64 = FDIVDrr [[COPY]], [[COPY1]]
|
|
; CHECK: %d0 = COPY [[FDIVDrr]]
|
|
%0(s64) = COPY %d0
|
|
%1(s64) = COPY %d1
|
|
%2(s64) = G_FDIV %0, %1
|
|
%d0 = COPY %2(s64)
|
|
...
|