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c660180f94
llvm-mirror/test/CodeGen/AArch64/GlobalISel
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Volkan Keles c660180f94 GlobalISel: Enable the legalization of G_MERGE_VALUES and G_UNMERGE_VALUES 
Summary: LegalizerInfo assumes all G_MERGE_VALUES and G_UNMERGE_VALUES instructions are legal, so it is not possible to legalize vector operations on illegal vector types. This patch fixes the problem by removing the related check and adding default actions for G_MERGE_VALUES and G_UNMERGE_VALUES.

Reviewers: qcolombet, ab, dsanders, aditya_nandakumar, t.p.northover, kristof.beyls

Reviewed By: dsanders

Subscribers: rovka, javed.absar, igorb, llvm-commits

Differential Revision: https://reviews.llvm.org/D39823

llvm-svn: 319524
2017-12-01 08:19:10 +00:00
..
arm64-callingconv-ios.ll MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
arm64-callingconv.ll MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
arm64-fallback.ll [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output 2017-11-30 12:12:19 +00:00
arm64-irtranslator-stackprotect.ll MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
arm64-irtranslator.ll [GlobalISel][IRTranslator] Fix crash during translation of zero sized loads/stores/args/returns. 2017-11-30 20:06:02 +00:00
arm64-regbankselect.mir [AArch64] Map G_LOAD on FPR when the definition goes to a copy to FPR 2017-11-18 04:28:59 +00:00
call-translator-ios.ll MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
call-translator.ll MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
combine-anyext-crash.mir [GlobalISel] Fix legalizer trying to process a deleted instruction. 2017-10-06 19:24:15 +00:00
debug-insts.ll [CodeGen] Always use printReg to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
dynamic-alloca.ll MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
gisel-abort.ll
gisel-commandline-option.ll
gisel-fail-intermediate-legalizer.ll
inline-asm.ll
irtranslator-bitcast.ll MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
irtranslator-exceptions.ll MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
legalize-add.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-and.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-atomicrmw.mir [aarch64][globalisel] Add missing tests from r319216 2017-11-28 20:27:59 +00:00
legalize-cmp.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-cmpxchg-with-success.mir [aarch64][globalisel] Legalize G_ATOMIC_CMPXCHG_WITH_SUCCESS and G_ATOMICRMW_* 2017-11-30 20:11:42 +00:00
legalize-cmpxchg.mir [aarch64][globalisel] Add missing tests from r319216 2017-11-28 20:27:59 +00:00
legalize-combines.mir GlobalISel: Enable the legalization of G_MERGE_VALUES and G_UNMERGE_VALUES 2017-12-01 08:19:10 +00:00
legalize-constant.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-div.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-exceptions.ll MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
legalize-ext.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-extracts.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-fcmp.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-fneg.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
legalize-fptoi.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-gep.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
legalize-ignore-non-generic.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
legalize-inserts.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-itofp.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-load-store.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-merge-values.mir GlobalISel: Enable the legalization of G_MERGE_VALUES and G_UNMERGE_VALUES 2017-12-01 08:19:10 +00:00
legalize-mul.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-nonpowerof2eltsvec.mir GlobalISel: Enable the legalization of G_MERGE_VALUES and G_UNMERGE_VALUES 2017-12-01 08:19:10 +00:00
legalize-or.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-phi.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-pow.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-property.mir
legalize-rem.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-shift.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-simple.mir [GISel]: DCE copy instructions during legalization 2017-11-17 02:44:55 +00:00
legalize-sub.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-undef.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-unmerge-values.mir GlobalISel: Enable the legalization of G_MERGE_VALUES and G_UNMERGE_VALUES 2017-12-01 08:19:10 +00:00
legalize-vaarg.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-xor.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
lit.local.cfg
localizer-in-O0-pipeline.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
localizer.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
no-regclass.mir GlobalISel: Enable the legalization of G_MERGE_VALUES and G_UNMERGE_VALUES 2017-12-01 08:19:10 +00:00
reg-bank-128bit.mir [GISel][AArch64]: Fix illegal Generic copies in tests 2017-10-23 22:53:04 +00:00
regbankselect-dbg-value.mir [CodeGen] Always use printReg to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
regbankselect-default.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
regbankselect-reg_sequence.mir
select-atomicrmw.mir [globalisel][tablegen] Add support for importing G_ATOMIC_CMPXCHG, G_ATOMICRMW_* rules from SelectionDAG. 2017-11-28 22:07:05 +00:00
select-binop.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-bitcast-bigendian.mir [globalisel][tablegen] Add support for multi-insn emission 2017-11-01 19:57:57 +00:00
select-bitcast.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-br.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-bswap.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-cbz.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-cmpxchg.mir [globalisel][tablegen] Add support for importing G_ATOMIC_CMPXCHG, G_ATOMICRMW_* rules from SelectionDAG. 2017-11-28 22:07:05 +00:00
select-constant.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-dbg-value.mir [CodeGen] Always use printReg to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
select-fma.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-fp-casts.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-imm.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-implicit-def.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-insert-extract.mir [MIRPrinter] Use %subreg.xxx syntax for subregister index operands 2017-11-06 21:46:06 +00:00
select-int-ext.mir [MIRPrinter] Use %subreg.xxx syntax for subregister index operands 2017-11-06 21:46:06 +00:00
select-int-ptr-casts.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-intrinsic-aarch64-hint.mir [globalisel] Add support for intrinsic_void 2017-09-19 13:23:01 +00:00
select-intrinsic-aarch64-sdiv.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-intrinsic-crypto-aesmc.mir [globalisel][tablegen] Add support for multi-insn emission 2017-11-01 19:57:57 +00:00
select-load.mir [globalisel][tablegen] Add support for extload. 2017-11-13 18:30:23 +00:00
select-muladd.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-neon-vcvtfxu2fp.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-phi.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-pr32733.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-property.mir
select-store.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-trunc.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-xor.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
translate-gep.ll MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
varargs-ios-translator.ll MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
vastart.ll MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
verify-regbankselected.mir [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output 2017-11-30 12:12:19 +00:00
verify-selected.mir [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output 2017-11-30 12:12:19 +00:00