mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-23 13:02:52 +02:00
491c957c8a
Summary: Print %subreg.<subregidxname> instead of just the subregister index when printing immediate operands corresponding to subreg indices in INSERT_SUBREG, EXTRACT_SUBREG, SUBREG_TO_REG and REG_SEQUENCE. Reviewers: qcolombet, MatzeB Reviewed By: MatzeB Subscribers: nhaehnle, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D39696 llvm-svn: 317513
261 lines
6.2 KiB
YAML
261 lines
6.2 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
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--- |
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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define void @anyext_s64_from_s32() { ret void }
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define void @anyext_s32_from_s8() { ret void }
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define void @zext_s64_from_s32() { ret void }
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define void @zext_s32_from_s16() { ret void }
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define void @zext_s32_from_s8() { ret void }
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define void @zext_s16_from_s8() { ret void }
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define void @sext_s64_from_s32() { ret void }
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define void @sext_s32_from_s16() { ret void }
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define void @sext_s32_from_s8() { ret void }
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define void @sext_s16_from_s8() { ret void }
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...
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---
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name: anyext_s64_from_s32
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.0:
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liveins: %w0
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; CHECK-LABEL: name: anyext_s64_from_s32
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; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %w0
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32
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; CHECK: [[COPY1:%[0-9]+]]:gpr64all = COPY [[SUBREG_TO_REG]]
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; CHECK: %x0 = COPY [[COPY1]]
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%0(s32) = COPY %w0
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%1(s64) = G_ANYEXT %0
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%x0 = COPY %1(s64)
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...
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---
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name: anyext_s32_from_s8
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.0:
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liveins: %w0
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; CHECK-LABEL: name: anyext_s32_from_s8
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
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; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
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; CHECK: %w0 = COPY [[COPY2]]
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%2:gpr(s32) = COPY %w0
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%0(s8) = G_TRUNC %2
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%1(s32) = G_ANYEXT %0
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%w0 = COPY %1(s32)
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...
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---
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name: zext_s64_from_s32
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.0:
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liveins: %w0
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; CHECK-LABEL: name: zext_s64_from_s32
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32
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; CHECK: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 31
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; CHECK: %x0 = COPY [[UBFMXri]]
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%0(s32) = COPY %w0
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%1(s64) = G_ZEXT %0
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%x0 = COPY %1(s64)
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...
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---
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name: zext_s32_from_s16
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.0:
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liveins: %w0
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; CHECK-LABEL: name: zext_s32_from_s16
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
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; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 0, 15
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; CHECK: %w0 = COPY [[UBFMWri]]
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%2:gpr(s32) = COPY %w0
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%0(s16) = G_TRUNC %2
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%1(s32) = G_ZEXT %0
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%w0 = COPY %1
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...
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---
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name: zext_s32_from_s8
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.0:
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liveins: %w0
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; CHECK-LABEL: name: zext_s32_from_s8
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
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; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 0, 15
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; CHECK: %w0 = COPY [[UBFMWri]]
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%2:gpr(s32) = COPY %w0
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%0(s16) = G_TRUNC %2
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%1(s32) = G_ZEXT %0
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%w0 = COPY %1(s32)
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...
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---
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name: zext_s16_from_s8
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.0:
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liveins: %w0
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; CHECK-LABEL: name: zext_s16_from_s8
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
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; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 0, 7
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; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[UBFMWri]]
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; CHECK: %w0 = COPY [[COPY2]]
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%2:gpr(s32) = COPY %w0
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%0(s8) = G_TRUNC %2
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%1(s16) = G_ZEXT %0
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%3:gpr(s32) = G_ANYEXT %1
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%w0 = COPY %3(s32)
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...
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---
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name: sext_s64_from_s32
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.0:
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liveins: %w0
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; CHECK-LABEL: name: sext_s64_from_s32
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32
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; CHECK: [[SBFMXri:%[0-9]+]]:gpr64 = SBFMXri [[SUBREG_TO_REG]], 0, 31
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; CHECK: %x0 = COPY [[SBFMXri]]
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%0(s32) = COPY %w0
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%1(s64) = G_SEXT %0
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%x0 = COPY %1(s64)
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...
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---
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name: sext_s32_from_s16
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.0:
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liveins: %w0
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; CHECK-LABEL: name: sext_s32_from_s16
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
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; CHECK: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY1]], 0, 15
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; CHECK: %w0 = COPY [[SBFMWri]]
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%2:gpr(s32) = COPY %w0
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%0(s16) = G_TRUNC %2
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%1(s32) = G_SEXT %0
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%w0 = COPY %1
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...
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---
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name: sext_s32_from_s8
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.0:
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liveins: %w0
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; CHECK-LABEL: name: sext_s32_from_s8
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
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; CHECK: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY1]], 0, 7
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; CHECK: %w0 = COPY [[SBFMWri]]
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%2:gpr(s32) = COPY %w0
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%0(s8) = G_TRUNC %2
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%1(s32) = G_SEXT %0
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%w0 = COPY %1(s32)
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...
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---
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name: sext_s16_from_s8
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.0:
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liveins: %w0
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; CHECK-LABEL: name: sext_s16_from_s8
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
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; CHECK: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY1]], 0, 7
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; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[SBFMWri]]
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; CHECK: %w0 = COPY [[COPY2]]
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%2:gpr(s32) = COPY %w0
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%0(s8) = G_TRUNC %2
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%1(s16) = G_SEXT %0
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%3:gpr(s32) = G_ANYEXT %1
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%w0 = COPY %3(s32)
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...
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