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8a9cdbd9d8
Assembler now permits pairs like 'v0:1', which are encoded differently from the odd-first pairs like 'v1:0'. The compiler will require more work to leverage these new register pairs.
135 lines
4.3 KiB
C++
135 lines
4.3 KiB
C++
//===- HexagonMCChecker.h - Instruction bundle checking ---------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements the checking of insns inside a bundle according to the
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// packet constraint rules of the Hexagon ISA.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCCHECKER_H
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#define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCCHECKER_H
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#include "MCTargetDesc/HexagonMCInstrInfo.h"
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#include "MCTargetDesc/HexagonMCTargetDesc.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/Support/SMLoc.h"
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#include <set>
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#include <utility>
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namespace llvm {
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class MCContext;
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class MCInst;
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class MCInstrInfo;
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class MCRegisterInfo;
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class MCSubtargetInfo;
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/// Check for a valid bundle.
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class HexagonMCChecker {
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MCContext &Context;
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MCInst &MCB;
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const MCRegisterInfo &RI;
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MCInstrInfo const &MCII;
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MCSubtargetInfo const &STI;
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bool ReportErrors;
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/// Set of definitions: register #, if predicated, if predicated true.
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using PredSense = std::pair<unsigned, bool>;
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static const PredSense Unconditional;
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using PredSet = std::multiset<PredSense>;
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using PredSetIterator = std::multiset<PredSense>::iterator;
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using DefsIterator = DenseMap<unsigned, PredSet>::iterator;
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DenseMap<unsigned, PredSet> Defs;
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/// Set of weak definitions whose clashes should be enforced selectively.
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using SoftDefsIterator = std::set<unsigned>::iterator;
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std::set<unsigned> SoftDefs;
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/// Set of temporary definitions not committed to the register file.
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using TmpDefsIterator = std::set<unsigned>::iterator;
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std::set<unsigned> TmpDefs;
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/// Set of new predicates used.
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using NewPredsIterator = std::set<unsigned>::iterator;
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std::set<unsigned> NewPreds;
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/// Set of predicates defined late.
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using LatePredsIterator = std::multiset<unsigned>::iterator;
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std::multiset<unsigned> LatePreds;
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/// Set of uses.
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using UsesIterator = std::set<unsigned>::iterator;
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std::set<unsigned> Uses;
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/// Pre-defined set of read-only registers.
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using ReadOnlyIterator = std::set<unsigned>::iterator;
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std::set<unsigned> ReadOnly;
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// Contains the vector-pair-registers with the even number
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// first ("v0:1", e.g.) used/def'd in this packet.
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std::set<unsigned> ReversePairs;
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void init();
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void init(MCInst const &);
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void initReg(MCInst const &, unsigned, unsigned &PredReg, bool &isTrue);
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bool registerUsed(unsigned Register);
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std::tuple<MCInst const *, unsigned, HexagonMCInstrInfo::PredicateInfo>
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registerProducer(unsigned Register,
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HexagonMCInstrInfo::PredicateInfo Predicated);
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// Checks performed.
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bool checkBranches();
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bool checkPredicates();
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bool checkNewValues();
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bool checkRegisters();
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bool checkRegistersReadOnly();
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void checkRegisterCurDefs();
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bool checkSolo();
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bool checkShuffle();
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bool checkSlots();
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bool checkAXOK();
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bool checkHWLoop();
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bool checkCOFMax1();
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bool checkLegalVecRegPair();
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static void compoundRegisterMap(unsigned &);
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bool isPredicateRegister(unsigned R) const {
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return (Hexagon::P0 == R || Hexagon::P1 == R || Hexagon::P2 == R ||
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Hexagon::P3 == R);
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}
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bool isLoopRegister(unsigned R) const {
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return (Hexagon::SA0 == R || Hexagon::LC0 == R || Hexagon::SA1 == R ||
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Hexagon::LC1 == R);
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}
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public:
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explicit HexagonMCChecker(MCContext &Context, MCInstrInfo const &MCII,
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MCSubtargetInfo const &STI, MCInst &mcb,
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const MCRegisterInfo &ri, bool ReportErrors = true);
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explicit HexagonMCChecker(HexagonMCChecker const &Check,
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MCSubtargetInfo const &STI, bool CopyReportErrors);
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bool check(bool FullCheck = true);
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void reportErrorRegisters(unsigned Register);
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void reportErrorNewValue(unsigned Register);
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void reportError(SMLoc Loc, Twine const &Msg);
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void reportNote(SMLoc Loc, Twine const &Msg);
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void reportError(Twine const &Msg);
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void reportWarning(Twine const &Msg);
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void reportBranchErrors();
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCCHECKER_H
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