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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-22 10:42:39 +01:00
llvm-mirror/lib/Target/Hexagon
2020-09-05 18:17:48 -05:00
..
AsmParser [MC] Fix memory leak when allocating MCInst with bump allocator 2020-08-03 16:08:26 -07:00
Disassembler [MC] Fix memory leak when allocating MCInst with bump allocator 2020-08-03 16:08:26 -07:00
MCTargetDesc [X86][MC][Target] Initial backend support a tune CPU to support -mtune 2020-08-14 15:31:50 -07:00
TargetInfo CMake: Make most target symbols hidden by default 2020-01-14 19:46:52 -08:00
BitTracker.cpp Change the INLINEASM_BR MachineInstr to be a non-terminating instruction. 2020-07-01 12:51:50 -04:00
BitTracker.h
CMakeLists.txt Move RDF from Hexagon to Codegen 2020-03-17 12:43:14 -07:00
Hexagon.h
Hexagon.td [TableGen] Support combining AssemblerPredicates with ORs 2020-03-13 17:13:51 +00:00
HexagonArch.h [Hexagon] Add support for Hexagon/HVX v67 ISA 2020-01-20 16:16:49 -06:00
HexagonAsmPrinter.cpp [MCStreamer] De-capitalize EmitValue EmitIntValue{,InHex} 2020-02-14 23:08:40 -08:00
HexagonAsmPrinter.h [AsmPrinter][MCStreamer] De-capitalize EmitInstruction and EmitCFI* 2020-02-13 22:08:55 -08:00
HexagonBitSimplify.cpp [Hexagon] Add support for Hexagon v67t microarchitecture (tiny core) 2020-01-21 11:35:10 -06:00
HexagonBitTracker.cpp [Alignment][NFC] Transition to MachineFrameInfo::getObjectAlign() 2020-04-01 14:08:28 +00:00
HexagonBitTracker.h
HexagonBlockRanges.cpp
HexagonBlockRanges.h
HexagonBranchRelaxation.cpp [Alignment][NFC] Deprecate Align::None() 2020-01-24 12:53:58 +01:00
HexagonCallingConv.td [Hexagon] Reducing minimum alignment requirement 2020-06-24 10:28:37 -05:00
HexagonCFGOptimizer.cpp
HexagonCommonGEP.cpp Fix several places that were calling verifyFunction or verifyModule without checking the return value. 2020-05-18 13:28:46 -07:00
HexagonConstExtenders.cpp [Hexagon] Add a target feature to disable compound instructions 2020-01-16 12:37:30 -06:00
HexagonConstPropagation.cpp Change the INLINEASM_BR MachineInstr to be a non-terminating instruction. 2020-07-01 12:51:50 -04:00
HexagonCopyToCombine.cpp [Pass] Ensure we don't include PassSupport.h or PassAnalysisSupport.h directly 2020-04-26 12:58:20 +01:00
HexagonDepArch.h [Hexagon] Add support for Hexagon v67t microarchitecture (tiny core) 2020-01-21 11:35:10 -06:00
HexagonDepArch.td [TableGen] Support combining AssemblerPredicates with ORs 2020-03-13 17:13:51 +00:00
HexagonDepDecoders.inc [Hexagon] Remove unused operand definitions: s10_0Imm and s10_6Imm 2020-01-23 09:38:54 -06:00
HexagonDepIICHVX.td [Hexagon] Add support for Hexagon/HVX v67 ISA 2020-01-20 16:16:49 -06:00
HexagonDepIICScalar.td [Hexagon] Add support for Hexagon v67t microarchitecture (tiny core) 2020-01-21 11:35:10 -06:00
HexagonDepInstrFormats.td [Hexagon] Add support for Hexagon/HVX v67 ISA 2020-01-20 16:16:49 -06:00
HexagonDepInstrInfo.td [Hexagon] Add support for Hexagon/HVX v67 ISA 2020-01-20 16:16:49 -06:00
HexagonDepITypes.h [Hexagon] Add support for Hexagon/HVX v67 ISA 2020-01-20 16:16:49 -06:00
HexagonDepITypes.td [Hexagon] Add support for Hexagon/HVX v67 ISA 2020-01-20 16:16:49 -06:00
HexagonDepMapAsm2Intrin.td [TableGen] Drop deprecated leading # operation (NOP) and replace ## with # 2020-04-25 16:26:45 -07:00
HexagonDepMappings.td [Hexagon] Add support for Hexagon/HVX v67 ISA 2020-01-20 16:16:49 -06:00
HexagonDepMask.h [Hexagon] Add support for Hexagon/HVX v67 ISA 2020-01-20 16:16:49 -06:00
HexagonDepOperands.td [Hexagon] Remove unused operand definitions: s10_0Imm and s10_6Imm 2020-01-23 09:38:54 -06:00
HexagonDepTimingClasses.h [Hexagon] Add support for Hexagon/HVX v67 ISA 2020-01-20 16:16:49 -06:00
HexagonEarlyIfConv.cpp MachineBasicBlock::updateTerminator now requires an explicit layout successor. 2020-06-06 22:30:51 -04:00
HexagonExpandCondsets.cpp Make more use of MachineInstr::mayLoadOrStore. 2019-12-19 11:51:52 +00:00
HexagonFixupHwLoops.cpp [Pass] Ensure we don't include PassSupport.h or PassAnalysisSupport.h directly 2020-04-26 12:58:20 +01:00
HexagonFrameLowering.cpp [MC] Change MCCFIInstruction::createDefCfa to cfiDefCfa which does not negate Offset 2020-05-22 15:47:26 -07:00
HexagonFrameLowering.h CodeGen: Use Register in TargetFrameLowering 2020-04-07 17:07:44 -04:00
HexagonGenExtract.cpp Fix HexagonGenExtract return status 2020-07-13 20:41:59 +02:00
HexagonGenInsert.cpp Reland 'Fixed -Wdeprecated-copy warnings. NFCI.' 2019-11-23 23:09:39 +01:00
HexagonGenMux.cpp [Hexagon] Validate the iterators before converting them to mux. 2019-11-14 13:01:16 -06:00
HexagonGenPredicate.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
HexagonHardwareLoops.cpp CodeGen: Convert some TII hooks to use Register 2020-04-03 14:52:54 -04:00
HexagonHazardRecognizer.cpp
HexagonHazardRecognizer.h
HexagonIICHVX.td
HexagonIICScalar.td [llvm] NFC: Fix trivial typo in rst and td files 2020-04-23 14:26:32 +09:00
HexagonInstrFormats.td [llvm] NFC: Fix trivial typo in rst and td files 2020-04-23 14:26:32 +09:00
HexagonInstrFormatsV60.td
HexagonInstrFormatsV65.td [llvm] NFC: Fix trivial typo in rst and td files 2020-04-23 14:26:32 +09:00
HexagonInstrInfo.cpp [Hexagon] Implement llvm.masked.load and llvm.masked.store for HVX 2020-08-26 13:10:22 -05:00
HexagonInstrInfo.h [AMDGPU/MemOpsCluster] Let mem ops clustering logic also consider number of clustered bytes 2020-06-01 22:52:34 +05:30
HexagonIntrinsics.td [TableGen] Drop deprecated leading # operation (NOP) and replace ## with # 2020-04-25 16:26:45 -07:00
HexagonIntrinsicsV5.td
HexagonIntrinsicsV60.td [Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1 2020-02-19 14:14:56 -06:00
HexagonISelDAGToDAG.cpp [Alignment][NFC] Use proper getter to retrieve alignment from ConstantInt and ConstantSDNode 2020-07-03 08:06:43 +00:00
HexagonISelDAGToDAG.h [Alignment][NFC] Use proper getter to retrieve alignment from ConstantInt and ConstantSDNode 2020-07-03 08:06:43 +00:00
HexagonISelDAGToDAGHVX.cpp [Hexagon] Fix perfect shuffle generation for single vectors 2020-08-30 06:43:16 -05:00
HexagonISelLowering.cpp [Hexagon] Handle widening of vector truncate 2020-09-05 15:07:38 -05:00
HexagonISelLowering.h [Hexagon] Handle widening of vector truncate 2020-09-05 15:07:38 -05:00
HexagonISelLoweringHVX.cpp [Hexagon] Resize the mem operand when widening loads and stores 2020-09-05 18:17:48 -05:00
HexagonLoopIdiomRecognition.cpp [SCEV] Move ScalarEvolutionExpander.cpp to Transforms/Utils (NFC). 2020-05-20 10:53:40 +01:00
HexagonMachineFunctionInfo.cpp
HexagonMachineFunctionInfo.h Add support for Linux/Musl ABI 2020-01-20 09:59:56 -06:00
HexagonMachineScheduler.cpp
HexagonMachineScheduler.h
HexagonMapAsm2IntrinV62.gen.td
HexagonMapAsm2IntrinV65.gen.td
HexagonMCInstLower.cpp [MC] Fix memory leak when allocating MCInst with bump allocator 2020-08-03 16:08:26 -07:00
HexagonNewValueJump.cpp [Hexagon][NFC] Remove redundant condition 2020-07-01 09:04:26 +02:00
HexagonOperands.td
HexagonOptAddrMode.cpp [RDF] Remove uses of RDFRegisters::normalize (deprecate) 2020-08-04 17:02:12 -05:00
HexagonOptimizeSZextends.cpp [IR] Split out target specific intrinsic enums into separate headers 2019-12-11 18:02:14 -08:00
HexagonPatterns.td [Hexagon] Correct the order of operands when lowering funnel shift-left 2020-07-28 21:22:41 -05:00
HexagonPatternsHVX.td [Hexagon] Handle widening of vector truncate 2020-09-05 15:07:38 -05:00
HexagonPatternsV65.td
HexagonPeephole.cpp [Pass] Ensure we don't include PassSupport.h or PassAnalysisSupport.h directly 2020-04-26 12:58:20 +01:00
HexagonPseudo.td [TableGen] Drop deprecated leading # operation (NOP) and replace ## with # 2020-04-25 16:26:45 -07:00
HexagonRDFOpt.cpp Move RDF from Hexagon to Codegen 2020-03-17 12:43:14 -07:00
HexagonRegisterInfo.cpp CodeGen: Use Register in TargetFrameLowering 2020-04-07 17:07:44 -04:00
HexagonRegisterInfo.h [TargetRegisterInfo] Default trackLivenessAfterRegAlloc() to true 2020-01-19 14:20:37 -08:00
HexagonRegisterInfo.td [Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1 2020-02-19 14:14:56 -06:00
HexagonSchedule.td [Hexagon] Add support for Hexagon v67t microarchitecture (tiny core) 2020-01-21 11:35:10 -06:00
HexagonScheduleV5.td
HexagonScheduleV55.td
HexagonScheduleV60.td
HexagonScheduleV62.td
HexagonScheduleV65.td
HexagonScheduleV66.td
HexagonScheduleV67.td [Hexagon] Add support for Hexagon/HVX v67 ISA 2020-01-20 16:16:49 -06:00
HexagonScheduleV67T.td [Hexagon] Add support for Hexagon v67t microarchitecture (tiny core) 2020-01-21 11:35:10 -06:00
HexagonSelectionDAGInfo.cpp [Alignment][NFC] Migrate SelectionDAGTargetInfo::EmitTargetCodeForMemcpy to Align 2020-06-30 13:12:31 +00:00
HexagonSelectionDAGInfo.h [Alignment][NFC] Migrate SelectionDAGTargetInfo::EmitTargetCodeForMemcpy to Align 2020-06-30 13:12:31 +00:00
HexagonSplitConst32AndConst64.cpp
HexagonSplitDouble.cpp CodeGen: Convert some TII hooks to use Register 2020-04-03 14:52:54 -04:00
HexagonStoreWidening.cpp [Alignment][NFC] Use Align version of getMachineMemOperand 2020-03-30 15:46:27 +00:00
HexagonSubtarget.cpp [X86][MC][Target] Initial backend support a tune CPU to support -mtune 2020-08-14 15:31:50 -07:00
HexagonSubtarget.h [X86][MC][Target] Initial backend support a tune CPU to support -mtune 2020-08-14 15:31:50 -07:00
HexagonTargetMachine.cpp [Attributes] Add a method to check if an Attribute has AttrKind None. Use instead of hasAttribute(Attribute::None) 2020-08-28 13:23:45 -07:00
HexagonTargetMachine.h
HexagonTargetObjectFile.cpp TargetLoweringObjectFile.h - remove unnecessary includes. NFCI. 2020-05-19 09:28:13 +01:00
HexagonTargetObjectFile.h TargetLoweringObjectFile.h - remove unnecessary includes. NFCI. 2020-05-19 09:28:13 +01:00
HexagonTargetStreamer.h [MC] De-capitalize another set of MCStreamer::Emit* functions 2020-02-14 19:26:52 -08:00
HexagonTargetTransformInfo.cpp [Hexagon] Implement llvm.masked.load and llvm.masked.store for HVX 2020-08-26 13:10:22 -05:00
HexagonTargetTransformInfo.h [Hexagon] Implement llvm.masked.load and llvm.masked.store for HVX 2020-08-26 13:10:22 -05:00
HexagonVectorLoopCarriedReuse.cpp [IR] Split out target specific intrinsic enums into separate headers 2019-12-11 18:02:14 -08:00
HexagonVectorPrint.cpp [Hexagon] v67+ HVX register pairs should support either direction 2020-02-14 12:43:43 -06:00
HexagonVExtract.cpp [Alignment][NFC] Migrate AArch64, ARM, Hexagon, MSP and NVPTX backends to Align 2020-06-30 07:56:17 +00:00
HexagonVLIWPacketizer.cpp [Target] Fix typos. NFC 2020-05-22 14:40:43 +02:00
HexagonVLIWPacketizer.h [Hexagon] Add support for Hexagon v67t microarchitecture (tiny core) 2020-01-21 11:35:10 -06:00
LLVMBuild.txt
RDFCopy.cpp Move RDF from Hexagon to Codegen 2020-03-17 12:43:14 -07:00
RDFCopy.h Move RDF from Hexagon to Codegen 2020-03-17 12:43:14 -07:00
RDFDeadCode.cpp Move RDF from Hexagon to Codegen 2020-03-17 12:43:14 -07:00
RDFDeadCode.h Move RDF from Hexagon to Codegen 2020-03-17 12:43:14 -07:00