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llvm-mirror/test/CodeGen/MIR
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Ahmed Bougacha e845469c16 [MIRParser] Allow generic register specification on operand. 
This completes r292321 by adding support for generic registers, e.g.:

  %2:_(s32) = G_ADD %0, %1

llvm-svn: 292550
2017-01-20 00:29:59 +00:00
..
AArch64 MIRParser: Allow regclass specification on operand 2017-01-18 00:59:19 +00:00
AMDGPU AMDGPU: Fix handling of 16-bit immediates 2016-12-10 00:39:12 +00:00
ARM Move test to correct directory 2016-12-17 02:16:26 +00:00
Generic [MIRPrinter] XFAIL test for powerpc 2016-11-18 20:08:05 +00:00
Hexagon Move .mir tests to appropriate directories 2016-12-09 19:08:15 +00:00
Mips MIRParser: Use shorter cfi identifiers 2016-07-26 18:20:00 +00:00
NVPTX llc: Add support for -run-pass none 2016-07-16 02:24:59 +00:00
PowerPC MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it. 2016-08-24 01:32:41 +00:00
X86 [MIRParser] Allow generic register specification on operand. 2017-01-20 00:29:59 +00:00
README Add README describing the intention of test/CodeGen/MIR 2016-12-09 20:16:12 +00:00

README 

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.