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llvm-mirror/test/CodeGen
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Matt Arsenault b3bd0133e4 AMDGPU: Don't wait at end of block with a trivial successor 
If there is only one successor, and that successor only
has one predecessor the wait can obviously be delayed until
uses or the end of the next block. This avoids code quality
regressions when there are trivial fallthrough blocks inserted
for structurization.

llvm-svn: 297251
2017-03-08 01:06:58 +00:00
..
AArch64 GlobalISel: use inserts for landingpad instead of sequences. 2017-03-07 23:04:06 +00:00
AMDGPU AMDGPU: Don't wait at end of block with a trivial successor 2017-03-08 01:06:58 +00:00
ARM [DAGCombine] Simplify ISD::AND in GetDemandedBits. 2017-03-08 00:56:35 +00:00
AVR [AVR] Disable integrated assembler for a few tests 2017-02-22 22:41:13 +00:00
BPF [SDAG] Revert r296476 (and r296486, r296668, r296690). 2017-03-03 10:02:25 +00:00
Generic Do not verify MachimeDominatorTree if it is not calculated 2017-03-02 12:00:10 +00:00
Hexagon [Hexagon] Check for presence before looking registers up in bit tracker 2017-03-07 23:12:04 +00:00
Inputs
Lanai
Mips [SDAG] Revert r296476 (and r296486, r296668, r296690). 2017-03-03 10:02:25 +00:00
MIR MIRTests: Remove unnecessary 2>&1 redirection 2017-02-22 18:47:41 +00:00
MSP430 [SDAG] Revert r296476 (and r296486, r296668, r296690). 2017-03-03 10:02:25 +00:00
NVPTX [NVPTX] Fixed lowering of unaligned loads/stores of f16 scalars and vectors. 2017-03-07 20:33:38 +00:00
PowerPC Revert "[PowerPC][ELFv2ABI] Allocate parameter area on-demand to reduce stack frame size" 2017-03-07 07:40:10 +00:00
SPARC Codegen: Make chains from trellis-shaped CFGs 2017-02-15 19:49:14 +00:00
SystemZ [SystemZ] Add check VT.isSimple() in canTreateAsByteVector() 2017-03-07 09:49:31 +00:00
Thumb In Thumb1, materialize a move between low registers as a movs, if CPSR isn't live. 2017-03-07 09:38:16 +00:00
Thumb2 [ARM] Replace HasT2ExtractPack with HasDSP 2017-02-17 15:42:44 +00:00
WebAssembly [WebAssembly] Convert the remaining unit tests to the new wasm-object-file target. 2017-02-28 23:37:04 +00:00
WinEH
X86 [DAGCombine] Simplify ISD::AND in GetDemandedBits. 2017-03-08 00:56:35 +00:00
XCore [SDAG] Revert r296476 (and r296486, r296668, r296690). 2017-03-03 10:02:25 +00:00