Bob Wilson cc87ed123c Set trunc store action to Expand for all X86 targets. ...

When compiling without SSE2, isTruncStoreLegal(F64, F32) would return Legal, whereas with SSE2 it would return Expand. And since the Target doesn't seem to actually handle a truncstore for double -> float, it would just output a store of a full double in the space for a float hence overwriting other bits on the stack.

Patch by Luqman Aden!

llvm-svn: 217410

2014-09-09 01:13:36 +00:00

..

AArch64

[AArch64] Improve AA to remove unneeded edges in the AA MI scheduling graph.

2014-09-08 14:43:48 +00:00

ARM

Missing test from r216989

2014-09-02 22:46:18 +00:00

CPP

IR: add "cmpxchg weak" variant to support permitted failure.

2014-06-13 14:24:07 +00:00

Generic

Add a regression test to sanity check the PBQP allocator.

2014-09-03 18:04:10 +00:00

Hexagon

DebugInfo: Assert that any CU for which debug_loc lists are emitted, has at least one range.

2014-08-06 00:21:25 +00:00

Inputs

…

Mips

Replace -use-init-array with -use-ctors.

2014-09-02 13:54:53 +00:00

MSP430

Do not assume the value passed to memset is an i32.

2014-08-29 08:23:53 +00:00

NVPTX

[MachineSink] Use the real post dominator tree

2014-09-01 03:47:25 +00:00

PowerPC

Enable splitting indexing from loads with TargetConstants

2014-09-02 16:05:23 +00:00

R600

R600/SI: Replace LDS atomics with no return versions

2014-09-08 15:07:31 +00:00

SPARC

IR: add "cmpxchg weak" variant to support permitted failure.

2014-06-13 14:24:07 +00:00

SystemZ

IR: add "cmpxchg weak" variant to support permitted failure.

2014-06-13 14:24:07 +00:00

Thumb

Check-label a bit more specific

2014-09-03 13:32:08 +00:00

Thumb2

ARM / x86_64 varargs: Don't save regparms in prologue without va_start

2014-08-22 21:59:26 +00:00

X86

Set trunc store action to Expand for all X86 targets.

2014-09-09 01:13:36 +00:00

XCore

llvm/test/CodeGen/XCore/dwarf_debug.ll: Fix not to be affected by *-win32.

2014-07-04 11:58:03 +00:00