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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-23 04:52:54 +02:00
llvm-mirror/test/CodeGen
2015-02-24 21:46:23 +00:00
..
AArch64 AArch64: Relax assert about large shift sizes. 2015-02-24 18:52:04 +00:00
ARM Added test case for PR22678 (check CONCAT_VECTORS DAG combiner pass doesn't introduce illegal types) 2015-02-24 21:46:23 +00:00
BPF
CPP
Generic
Hexagon [Hexagon] Factoring classes out of store patterns. 2015-02-09 20:33:46 +00:00
Inputs
Mips Beginning of alloca implementation for Mips fast-isel 2015-02-24 02:36:45 +00:00
MSP430
NVPTX [NVPTX] Emit .pragma "nounroll" for loops marked with nounroll 2015-02-01 02:27:45 +00:00
PowerPC I incorrectly marked the VORC instruction as isCommutable when I added it. 2015-02-20 15:54:58 +00:00
R600 R600/SI: Remove isel mubuf legalization 2015-02-24 17:59:19 +00:00
SPARC SelectionDAG: fold (fp_to_u/sint (s/uint_to_fp)) here too 2015-02-16 21:47:58 +00:00
SystemZ [SystemZ] Support all TLS access models - CodeGen part 2015-02-18 09:13:27 +00:00
Thumb
Thumb2 Make buildbots better. 2015-02-11 12:24:09 +00:00
X86 Fixing eol-style 2015-02-24 20:49:35 +00:00
XCore Revert r229944: EH: Prune unreachable resume instructions during Dwarf EH preparation 2015-02-20 02:15:36 +00:00