..
AsmParser
[MC] De-capitalize another set of MCStreamer::Emit* functions
2020-02-14 19:26:52 -08:00
Disassembler
MCTargetDesc
[NFC][RISCV] Fixing typo in comment.
2020-02-05 11:30:11 -08:00
TargetInfo
Utils
CMakeLists.txt
LLVMBuild.txt
RISCV.h
RISCV.td
[TableGen] Support combining AssemblerPredicates with ORs
2020-03-13 17:13:51 +00:00
RISCVAsmPrinter.cpp
[RISCV] Compress instructions based on function features
2020-02-28 11:52:55 +00:00
RISCVCallingConv.td
RISCVCallLowering.cpp
RISCVCallLowering.h
RISCVExpandPseudoInsts.cpp
RISCVFrameLowering.cpp
[Alignment][NFC] Deprecate getMaxAlignment
2020-03-18 14:48:45 +01:00
RISCVFrameLowering.h
ArrayRef'ize restoreCalleeSavedRegisters. NFCI.
2020-02-29 09:50:23 +01:00
RISCVInstrFormats.td
RISCVInstrFormatsC.td
RISCVInstrInfo.cpp
RISCVInstrInfo.h
RISCVInstrInfo.td
[RISCV] Add new SchedRead SchedWrite
2020-03-10 00:12:27 +08:00
RISCVInstrInfoA.td
RISCVInstrInfoC.td
RISCVInstrInfoD.td
[RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w
2020-03-20 09:42:24 +00:00
RISCVInstrInfoF.td
[RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w
2020-03-20 09:42:24 +00:00
RISCVInstrInfoM.td
RISCVInstructionSelector.cpp
RISCVISelDAGToDAG.cpp
RISCVISelLowering.cpp
[RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w
2020-03-20 09:42:24 +00:00
RISCVISelLowering.h
[RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w
2020-03-20 09:42:24 +00:00
RISCVLegalizerInfo.cpp
RISCVLegalizerInfo.h
RISCVMachineFunctionInfo.h
[RISCV] Add support for save/restore of callee-saved registers via libcalls
2020-02-11 21:23:03 +00:00
RISCVMCInstLower.cpp
RISCVMergeBaseOffset.cpp
RISCVRegisterBankInfo.cpp
Revert "[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes"
2020-03-20 11:02:50 +01:00
RISCVRegisterBankInfo.h
Revert "[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes"
2020-03-20 11:02:50 +01:00
RISCVRegisterBanks.td
RISCVRegisterInfo.cpp
[RISCV] Correct the CallPreservedMask for the function call in an interrupt handler
2020-02-15 09:14:04 +08:00
RISCVRegisterInfo.h
[RISCV] Add support for save/restore of callee-saved registers via libcalls
2020-02-11 21:23:03 +00:00
RISCVRegisterInfo.td
RISCVSchedRocket32.td
[RISCV] Add new SchedRead SchedWrite
2020-03-10 00:12:27 +08:00
RISCVSchedRocket64.td
[RISCV] Add new SchedRead SchedWrite
2020-03-10 00:12:27 +08:00
RISCVSchedule.td
[RISCV] Add new SchedRead SchedWrite
2020-03-10 00:12:27 +08:00
RISCVSubtarget.cpp
Revert "[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes"
2020-03-20 11:02:50 +01:00
RISCVSubtarget.h
[RISCV] Add support for save/restore of callee-saved registers via libcalls
2020-02-11 21:23:03 +00:00
RISCVSystemOperands.td
RISCVTargetMachine.cpp
RISCVTargetMachine.h
RISCVTargetObjectFile.cpp
[X86] Reland D71360 Clean up UseInitArray initialization for X86ELFTargetObjectFile
2020-03-20 11:18:36 -07:00
RISCVTargetObjectFile.h
RISCVTargetTransformInfo.cpp
RISCVTargetTransformInfo.h
