mirror of
https://github.com/RPCS3/llvm-mirror.git
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54ff49aca5
Summary: Extend analysis forwarding loads from preceeding stores to work with extended loads and truncated stores to the same address so long as the load is fully subsumed by the store. Hexagon's swp-epilog-phis.ll and swp-memrefs-epilog1.ll test are deleted as they've no longer seem to be relevant. Reviewers: RKSimon, rnk, kparzysz, javed.absar Subscribers: sdardis, nemanjai, hiraditya, atanasyan, llvm-commits Differential Revision: https://reviews.llvm.org/D49200 llvm-svn: 344142
271 lines
7.5 KiB
LLVM
271 lines
7.5 KiB
LLVM
; RUN: llc -march=mipsel -pre-RA-sched=source < %s | FileCheck %s
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; All test functions do the same thing - they return the first variable
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; argument.
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; All CHECK's do the same thing - they check whether variable arguments from
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; registers are placed on correct stack locations, and whether the first
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; variable argument is returned from the correct stack location.
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declare void @llvm.va_start(i8*) nounwind
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declare void @llvm.va_end(i8*) nounwind
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; return int
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define i32 @va1(i32 %a, ...) nounwind {
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entry:
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%a.addr = alloca i32, align 4
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%ap = alloca i8*, align 4
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%b = alloca i32, align 4
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store i32 %a, i32* %a.addr, align 4
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%ap1 = bitcast i8** %ap to i8*
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call void @llvm.va_start(i8* %ap1)
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%0 = va_arg i8** %ap, i32
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store i32 %0, i32* %b, align 4
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%ap2 = bitcast i8** %ap to i8*
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call void @llvm.va_end(i8* %ap2)
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%tmp = load i32, i32* %b, align 4
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ret i32 %tmp
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; CHECK-LABEL: va1:
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; CHECK: addiu $sp, $sp, -16
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; CHECK: sw $7, 28($sp)
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; CHECK: sw $6, 24($sp)
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; CHECK: sw $5, 20($sp)
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; CHECK: move $2, $5
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}
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; check whether the variable double argument will be accessed from the 8-byte
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; aligned location (i.e. whether the address is computed by adding 7 and
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; clearing lower 3 bits)
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define double @va2(i32 %a, ...) nounwind {
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entry:
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%a.addr = alloca i32, align 4
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%ap = alloca i8*, align 4
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%b = alloca double, align 8
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store i32 %a, i32* %a.addr, align 4
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%ap1 = bitcast i8** %ap to i8*
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call void @llvm.va_start(i8* %ap1)
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%0 = va_arg i8** %ap, double
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store double %0, double* %b, align 8
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%ap2 = bitcast i8** %ap to i8*
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call void @llvm.va_end(i8* %ap2)
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%tmp = load double, double* %b, align 8
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ret double %tmp
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; CHECK-LABEL: va2:
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; CHECK: addiu $sp, $sp, -16
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; CHECK: sw $7, 28($sp)
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; CHECK: sw $6, 24($sp)
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; CHECK: sw $5, 20($sp)
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; CHECK: addiu $[[R0:[0-9]+]], $sp, 20
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; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
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; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
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; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
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; CHECK: ldc1 $f0, 0($[[R3]])
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}
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; int
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define i32 @va3(double %a, ...) nounwind {
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entry:
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%a.addr = alloca double, align 8
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%ap = alloca i8*, align 4
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%b = alloca i32, align 4
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store double %a, double* %a.addr, align 8
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%ap1 = bitcast i8** %ap to i8*
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call void @llvm.va_start(i8* %ap1)
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%0 = va_arg i8** %ap, i32
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store i32 %0, i32* %b, align 4
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%ap2 = bitcast i8** %ap to i8*
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call void @llvm.va_end(i8* %ap2)
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%tmp = load i32, i32* %b, align 4
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ret i32 %tmp
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; CHECK-LABEL: va3:
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; CHECK: addiu $sp, $sp, -16
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; CHECK: sw $7, 28($sp)
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; CHECK: sw $6, 24($sp)
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; CHECK: move $2, $6
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}
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; double
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define double @va4(double %a, ...) nounwind {
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entry:
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%a.addr = alloca double, align 8
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%ap = alloca i8*, align 4
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%b = alloca double, align 8
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store double %a, double* %a.addr, align 8
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%ap1 = bitcast i8** %ap to i8*
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call void @llvm.va_start(i8* %ap1)
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%0 = va_arg i8** %ap, double
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store double %0, double* %b, align 8
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%ap2 = bitcast i8** %ap to i8*
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call void @llvm.va_end(i8* %ap2)
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%tmp = load double, double* %b, align 8
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ret double %tmp
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; CHECK-LABEL: va4:
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; CHECK: addiu $sp, $sp, -24
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; CHECK: sw $7, 36($sp)
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; CHECK: sw $6, 32($sp)
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; CHECK: addiu ${{[0-9]+}}, $sp, 32
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; CHECK: ldc1 $f0, 32($sp)
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}
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; int
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define i32 @va5(i32 %a, i32 %b, i32 %c, ...) nounwind {
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entry:
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%a.addr = alloca i32, align 4
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%b.addr = alloca i32, align 4
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%c.addr = alloca i32, align 4
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%ap = alloca i8*, align 4
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%d = alloca i32, align 4
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store i32 %a, i32* %a.addr, align 4
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store i32 %b, i32* %b.addr, align 4
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store i32 %c, i32* %c.addr, align 4
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%ap1 = bitcast i8** %ap to i8*
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call void @llvm.va_start(i8* %ap1)
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%0 = va_arg i8** %ap, i32
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store i32 %0, i32* %d, align 4
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%ap2 = bitcast i8** %ap to i8*
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call void @llvm.va_end(i8* %ap2)
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%tmp = load i32, i32* %d, align 4
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ret i32 %tmp
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; CHECK-LABEL: va5:
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; CHECK: addiu $sp, $sp, -24
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; CHECK: sw $7, 36($sp)
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; CHECK: move $2, $7
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}
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; double
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define double @va6(i32 %a, i32 %b, i32 %c, ...) nounwind {
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entry:
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%a.addr = alloca i32, align 4
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%b.addr = alloca i32, align 4
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%c.addr = alloca i32, align 4
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%ap = alloca i8*, align 4
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%d = alloca double, align 8
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store i32 %a, i32* %a.addr, align 4
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store i32 %b, i32* %b.addr, align 4
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store i32 %c, i32* %c.addr, align 4
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%ap1 = bitcast i8** %ap to i8*
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call void @llvm.va_start(i8* %ap1)
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%0 = va_arg i8** %ap, double
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store double %0, double* %d, align 8
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%ap2 = bitcast i8** %ap to i8*
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call void @llvm.va_end(i8* %ap2)
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%tmp = load double, double* %d, align 8
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ret double %tmp
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; CHECK-LABEL: va6:
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; CHECK: addiu $sp, $sp, -24
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; CHECK: sw $7, 36($sp)
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; CHECK: addiu $[[R0:[0-9]+]], $sp, 36
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; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
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; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
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; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
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; CHECK: ldc1 $f0, 0($[[R3]])
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}
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; int
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define i32 @va7(i32 %a, double %b, ...) nounwind {
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entry:
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%a.addr = alloca i32, align 4
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%b.addr = alloca double, align 8
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%ap = alloca i8*, align 4
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%c = alloca i32, align 4
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store i32 %a, i32* %a.addr, align 4
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store double %b, double* %b.addr, align 8
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%ap1 = bitcast i8** %ap to i8*
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call void @llvm.va_start(i8* %ap1)
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%0 = va_arg i8** %ap, i32
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store i32 %0, i32* %c, align 4
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%ap2 = bitcast i8** %ap to i8*
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call void @llvm.va_end(i8* %ap2)
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%tmp = load i32, i32* %c, align 4
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ret i32 %tmp
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; CHECK-LABEL: va7:
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; CHECK: addiu $sp, $sp, -24
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; CHECK: lw $2, 40($sp)
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}
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; double
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define double @va8(i32 %a, double %b, ...) nounwind {
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entry:
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%a.addr = alloca i32, align 4
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%b.addr = alloca double, align 8
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%ap = alloca i8*, align 4
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%c = alloca double, align 8
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store i32 %a, i32* %a.addr, align 4
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store double %b, double* %b.addr, align 8
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%ap1 = bitcast i8** %ap to i8*
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call void @llvm.va_start(i8* %ap1)
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%0 = va_arg i8** %ap, double
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store double %0, double* %c, align 8
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%ap2 = bitcast i8** %ap to i8*
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call void @llvm.va_end(i8* %ap2)
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%tmp = load double, double* %c, align 8
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ret double %tmp
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; CHECK-LABEL: va8:
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; CHECK: addiu $sp, $sp, -32
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; CHECK: addiu ${{[0-9]+}}, $sp, 48
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; CHECK: ldc1 $f0, 48($sp)
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}
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; int
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define i32 @va9(double %a, double %b, i32 %c, ...) nounwind {
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entry:
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%a.addr = alloca double, align 8
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%b.addr = alloca double, align 8
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%c.addr = alloca i32, align 4
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%ap = alloca i8*, align 4
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%d = alloca i32, align 4
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store double %a, double* %a.addr, align 8
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store double %b, double* %b.addr, align 8
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store i32 %c, i32* %c.addr, align 4
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%ap1 = bitcast i8** %ap to i8*
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call void @llvm.va_start(i8* %ap1)
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%0 = va_arg i8** %ap, i32
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store i32 %0, i32* %d, align 4
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%ap2 = bitcast i8** %ap to i8*
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call void @llvm.va_end(i8* %ap2)
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%tmp = load i32, i32* %d, align 4
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ret i32 %tmp
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; CHECK-LABEL: va9:
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; CHECK: addiu $sp, $sp, -24
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; CHECK: lw $2, 44($sp)
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}
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; double
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define double @va10(double %a, double %b, i32 %c, ...) nounwind {
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entry:
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%a.addr = alloca double, align 8
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%b.addr = alloca double, align 8
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%c.addr = alloca i32, align 4
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%ap = alloca i8*, align 4
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%d = alloca double, align 8
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store double %a, double* %a.addr, align 8
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store double %b, double* %b.addr, align 8
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store i32 %c, i32* %c.addr, align 4
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%ap1 = bitcast i8** %ap to i8*
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call void @llvm.va_start(i8* %ap1)
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%0 = va_arg i8** %ap, double
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store double %0, double* %d, align 8
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%ap2 = bitcast i8** %ap to i8*
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call void @llvm.va_end(i8* %ap2)
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%tmp = load double, double* %d, align 8
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ret double %tmp
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; CHECK-LABEL: va10:
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; CHECK: addiu $sp, $sp, -32
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; CHECK: addiu $[[R0:[0-9]+]], $sp, 52
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; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
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; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
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; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
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; CHECK: ldc1 $f0, 0($[[R3]])
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}
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