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e5bc3127f3
This patch exploits the xxsplti32dx instruction available on Power10 in place of constant pool loads where xxspltidp would not be able to, usually because the immediate cannot fit into 32 bits. Differential Revision: https://reviews.llvm.org/D95458
60 lines
2.0 KiB
LLVM
60 lines
2.0 KiB
LLVM
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s --check-prefix=CHECK-S
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; RUN: llc -verify-machineinstrs -target-abi=elfv2 -mtriple=powerpc64-- \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
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; RUN: --filetype=obj < %s | \
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; RUN: llvm-objdump --mcpu=pwr10 -dr - | FileCheck %s --check-prefix=CHECK-O
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; Constant Pool Index.
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; CHECK-S-LABEL: ConstPool
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; CHECK-S: xxsplti32dx vs1, 0, 1081002676
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; CHECK-S-NEXT: xxsplti32dx vs1, 1, 962072674
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; CHECK-S: blr
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; CHECK-O-LABEL: ConstPool
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; CHECK-O: xxsplti32dx 1, 0, 1081002676
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; CHECK-O-NEXT: xxsplti32dx 1, 1, 962072674
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; CHECK-O-NEXT: blr
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define dso_local double @ConstPool() local_unnamed_addr {
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entry:
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ret double 0x406ECAB439581062
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}
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@valIntLoc = common dso_local local_unnamed_addr global i32 0, align 4
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define dso_local signext i32 @ReadLocalVarInt() local_unnamed_addr {
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; CHECK-S-LABEL: ReadLocalVarInt
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; CHECK-S: # %bb.0: # %entry
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; CHECK-S-NEXT: plwa r3, valIntLoc@PCREL(0), 1
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; CHECK-S-NEXT: blr
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; CHECK-O-LABEL: ReadLocalVarInt
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; CHECK-O: plwa 3, 0(0), 1
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; CHECK-O-NEXT: R_PPC64_PCREL34 valIntLoc
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; CHECK-O-NEXT: blr
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entry:
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%0 = load i32, i32* @valIntLoc, align 4
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ret i32 %0
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}
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@valIntGlob = external global i32, align 4
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define dso_local signext i32 @ReadGlobalVarInt() local_unnamed_addr {
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; CHECK-S-LABEL: ReadGlobalVarInt
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; CHECK-S: # %bb.0: # %entry
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; CHECK-S-NEXT: pld r3, valIntGlob@got@pcrel(0), 1
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; CHECK-S-NEXT: .Lpcrel0:
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; CHECK-S-NEXT: .reloc .Lpcrel0-8,R_PPC64_PCREL_OPT,.-(.Lpcrel0-8)
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; CHECK-S-NEXT: lwa r3, 0(r3)
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; CHECK-S-NEXT: blr
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; CHECK-O-LABEL: ReadGlobalVarInt
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; CHECK-O: pld 3, 0(0), 1
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; CHECK-O-NEXT: R_PPC64_GOT_PCREL34 valIntGlob
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; CHECK-O-NEXT: R_PPC64_PCREL_OPT *ABS*+0x8
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; CHECK-O-NEXT: lwa 3, 0(3)
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; CHECK-O-NEXT: blr
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entry:
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%0 = load i32, i32* @valIntGlob, align 4
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ret i32 %0
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}
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