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f83e7bf498
Summary: Some constants can be handled with less instructions than our current results. And it seems our original approach is not very easy to extend. Therefore this patch proposes to materialize all 64-bit constants by enumerated patterns. I traversed almost all constants to verified the functionality of these pattens. A traversed comparison of the number of instructions used by the original method and the new method has also been completed, where no degradation was caused by this patch. This patch also passed Bootstrap test and SPEC test. Improvements of this patch are shown in llvm/test/CodeGen/PowerPC/constants-i64.ll Reviewed By: steven.zhang, stefanp Differential Revision: https://reviews.llvm.org/D92089
48 lines
1.4 KiB
LLVM
48 lines
1.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\
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; RUN: -mcpu=pwr9 --ppc-enable-pipeliner | FileCheck %s
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define void @lame_encode_buffer_interleaved() local_unnamed_addr {
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; CHECK-LABEL: lame_encode_buffer_interleaved:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lha 3, 0(3)
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; CHECK-NEXT: li 5, 1
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; CHECK-NEXT: lhz 4, 0(0)
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; CHECK-NEXT: rldic 5, 5, 62, 1
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; CHECK-NEXT: mtctr 5
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; CHECK-NEXT: srawi 3, 3, 1
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; CHECK-NEXT: addze 3, 3
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: .LBB0_1:
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; CHECK-NEXT: extsh 4, 4
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; CHECK-NEXT: srawi 4, 4, 1
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; CHECK-NEXT: addze 4, 4
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; CHECK-NEXT: bdnz .LBB0_1
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; CHECK-NEXT: # %bb.2:
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; CHECK-NEXT: sth 4, 0(0)
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; CHECK-NEXT: sth 3, 0(3)
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; CHECK-NEXT: blr
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br label %1
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1: ; preds = %1, %0
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%2 = phi i64 [ 0, %0 ], [ %13, %1 ]
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%3 = load i16, i16* null, align 2
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%4 = load i16, i16* undef, align 2
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%5 = sext i16 %3 to i32
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%6 = sext i16 %4 to i32
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%7 = add nsw i32 0, %5
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%8 = add nsw i32 0, %6
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%9 = sdiv i32 %7, 2
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%10 = sdiv i32 %8, 2
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%11 = trunc i32 %9 to i16
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%12 = trunc i32 %10 to i16
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store i16 %11, i16* null, align 2
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store i16 %12, i16* undef, align 2
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%13 = add i64 %2, 4
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%14 = icmp eq i64 %13, 0
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br i1 %14, label %15, label %1
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15: ; preds = %1
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ret void
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}
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