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llvm-mirror/test/CodeGen/PowerPC/xray-tail-call-sled.ll
Fangrui Song 21cd444174 [XRay] Change ARM/AArch64/powerpc64le to use version 2 sled (PC-relative address)
Follow-up of D78082 (x86-64).

This change avoids dynamic relocations in `xray_instr_map` for ARM/AArch64/powerpc64le.

MIPS64 cannot use 64-bit PC-relative addresses because R_MIPS_PC64 is not defined.
Because MIPS32 shares the same code, for simplicity, we don't use PC-relative addresses for MIPS32 as well.

Tested on AArch64 Linux and ppc64le Linux.

Reviewed By: ianlevesque

Differential Revision: https://reviews.llvm.org/D78590
2020-04-24 08:35:43 -07:00

45 lines
1.3 KiB
LLVM

; RUN: llc -filetype=asm -relocation-model=pic -o - -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
define i32 @callee() nounwind noinline uwtable "function-instrument"="xray-always" {
; CHECK-LABEL: .Ltmp0:
; CHECK: b .Ltmp1
; CHECK-NEXT: nop
; CHECK-NEXT: std 0, -8(1)
; CHECK-NEXT: mflr 0
; CHECK-NEXT: bl __xray_FunctionEntry
; CHECK-NEXT: nop
; CHECK-NEXT: mtlr 0
; CHECK-LABEL: .Ltmp1:
ret i32 0
; CHECK-LABEL: .Ltmp2:
; CHECK: blr
; CHECK-NEXT: nop
; CHECK-NEXT: std 0, -8(1)
; CHECK-NEXT: mflr 0
; CHECK-NEXT: bl __xray_FunctionExit
; CHECK-NEXT: nop
; CHECK-NEXT: mtlr 0
}
define i32 @caller() nounwind noinline uwtable "function-instrument"="xray-always" {
; CHECK-LABEL: .Ltmp5:
; CHECK-NEXT: b .Ltmp6
; CHECK-NEXT: nop
; CHECK-NEXT: std 0, -8(1)
; CHECK-NEXT: mflr 0
; CHECK-NEXT: bl __xray_FunctionEntry
; CHECK-NEXT: nop
; CHECK-NEXT: mtlr 0
; CHECK-LABEL: .Ltmp6:
%retval = tail call i32 @callee()
ret i32 %retval
; CHECK-LABEL: .Ltmp7:
; CHECK: blr
; CHECK-NEXT: nop
; CHECK-NEXT: std 0, -8(1)
; CHECK-NEXT: mflr 0
; CHECK-NEXT: bl __xray_FunctionExit
; CHECK-NEXT: nop
; CHECK-NEXT: mtlr 0
}