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21cd444174
Follow-up of D78082 (x86-64). This change avoids dynamic relocations in `xray_instr_map` for ARM/AArch64/powerpc64le. MIPS64 cannot use 64-bit PC-relative addresses because R_MIPS_PC64 is not defined. Because MIPS32 shares the same code, for simplicity, we don't use PC-relative addresses for MIPS32 as well. Tested on AArch64 Linux and ppc64le Linux. Reviewed By: ianlevesque Differential Revision: https://reviews.llvm.org/D78590
45 lines
1.3 KiB
LLVM
45 lines
1.3 KiB
LLVM
; RUN: llc -filetype=asm -relocation-model=pic -o - -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
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define i32 @callee() nounwind noinline uwtable "function-instrument"="xray-always" {
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; CHECK-LABEL: .Ltmp0:
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; CHECK: b .Ltmp1
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; CHECK-NEXT: nop
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; CHECK-NEXT: std 0, -8(1)
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; CHECK-NEXT: mflr 0
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; CHECK-NEXT: bl __xray_FunctionEntry
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; CHECK-NEXT: nop
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; CHECK-NEXT: mtlr 0
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; CHECK-LABEL: .Ltmp1:
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ret i32 0
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; CHECK-LABEL: .Ltmp2:
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; CHECK: blr
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; CHECK-NEXT: nop
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; CHECK-NEXT: std 0, -8(1)
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; CHECK-NEXT: mflr 0
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; CHECK-NEXT: bl __xray_FunctionExit
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; CHECK-NEXT: nop
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; CHECK-NEXT: mtlr 0
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}
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define i32 @caller() nounwind noinline uwtable "function-instrument"="xray-always" {
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; CHECK-LABEL: .Ltmp5:
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; CHECK-NEXT: b .Ltmp6
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; CHECK-NEXT: nop
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; CHECK-NEXT: std 0, -8(1)
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; CHECK-NEXT: mflr 0
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; CHECK-NEXT: bl __xray_FunctionEntry
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; CHECK-NEXT: nop
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; CHECK-NEXT: mtlr 0
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; CHECK-LABEL: .Ltmp6:
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%retval = tail call i32 @callee()
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ret i32 %retval
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; CHECK-LABEL: .Ltmp7:
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; CHECK: blr
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; CHECK-NEXT: nop
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; CHECK-NEXT: std 0, -8(1)
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; CHECK-NEXT: mflr 0
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; CHECK-NEXT: bl __xray_FunctionExit
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; CHECK-NEXT: nop
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; CHECK-NEXT: mtlr 0
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}
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