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llvm-mirror/test/MC/Disassembler
Bill Schmidt d115a77d30 [PPC64] Add vector pack/unpack support from ISA 2.07
This patch adds support for the following new instructions in the
Power ISA 2.07:

  vpksdss
  vpksdus
  vpkudus
  vpkudum
  vupkhsw
  vupklsw

These instructions are available through the vec_packs, vec_packsu,
vec_unpackh, and vec_unpackl built-in interfaces.  These are
lane-sensitive instructions, so the built-ins have different
implementations for big- and little-endian, and the instructions must
be marked as killing the vector swap optimization for now.

The first three instructions perform saturating pack operations.  The
fourth performs a modulo pack operation, which means it can be
represented with a vector shuffle, and conversely the appropriate
vector shuffles may cause this instruction to be generated.  The other
instructions are only generated via built-in support for now.

Appropriate tests have been added.

There is a companion patch to clang for the rest of this support.

llvm-svn: 237499
2015-05-16 01:02:12 +00:00
..
AArch64 AArch64: add BFC alias for the BFI/BFM instructions. 2015-04-30 18:28:58 +00:00
ARM [ARM] Add v8.1a "Privileged Access Never" extension 2015-04-16 11:34:25 +00:00
Hexagon [Hexagon] Adding missing vector multiply instruction encodings. Converting multiply intrinsics and updating tests. 2015-02-03 19:15:11 +00:00
Mips [mips][microMIPSr6] Implement CLO and CLZ instructions 2015-05-13 14:18:11 +00:00
PowerPC [PPC64] Add vector pack/unpack support from ISA 2.07 2015-05-16 01:02:12 +00:00
Sparc Sparc: Prefer reg+reg address encoding when only one register used. 2015-04-29 14:54:44 +00:00
SystemZ [SystemZ] Add z13 vector facility and MC support 2015-05-05 19:23:40 +00:00
X86 [X86] Fix PR23271 - RIP-relative decoding bug in disassembler. 2015-05-13 22:44:52 +00:00
XCore Reduce verbiage of lit.local.cfg files 2014-06-09 22:42:55 +00:00