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d4c615be8c
Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
36 lines
1.0 KiB
YAML
36 lines
1.0 KiB
YAML
# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass machine-scheduler -verify-machineinstrs -o - %s | FileCheck %s
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--- |
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define i64 @load_imp-def(i64* nocapture %P, i32 %v) {
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entry:
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%0 = bitcast i64* %P to i32*
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%1 = load i32, i32* %0
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%conv = zext i32 %1 to i64
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%arrayidx19 = getelementptr inbounds i64, i64* %P, i64 1
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%arrayidx1 = bitcast i64* %arrayidx19 to i32*
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store i32 %v, i32* %arrayidx1
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%2 = load i64, i64* %arrayidx19
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%and = and i64 %2, 4294967295
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%add = add nuw nsw i64 %and, %conv
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ret i64 %add
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}
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...
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---
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# CHECK-LABEL: name: load_imp-def
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# CHECK: bb.0.entry:
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# CHECK: LDRWui $x0, 0
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# CHECK: LDRWui $x0, 1
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# CHECK: STRWui $w1, $x0, 2
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name: load_imp-def
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $w1, $x0
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$w8 = LDRWui $x0, 1, implicit-def $x8 :: (load 4 from %ir.0)
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STRWui killed $w1, $x0, 2 :: (store 4 into %ir.arrayidx1)
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$w9 = LDRWui killed $x0, 0, implicit-def $x9 :: (load 4 from %ir.arrayidx19, align 8)
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$x0 = ADDXrr killed $x9, killed $x8
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RET_ReallyLR implicit $x0
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...
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