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1ba71f37a4
Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Krzysztof Parzyszek llvm-svn: 325697
94 lines
2.0 KiB
LLVM
94 lines
2.0 KiB
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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target triple = "hexagon-unknown--elf"
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; CHECK-LABEL: mul_1
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; CHECK: r1:0 = mpy(r2,r0)
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define i64 @mul_1(i64 %a0, i64 %a1) #0 {
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b2:
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%v3 = shl i64 %a0, 32
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%v4 = ashr exact i64 %v3, 32
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%v5 = shl i64 %a1, 32
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%v6 = ashr exact i64 %v5, 32
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%v7 = mul nsw i64 %v6, %v4
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ret i64 %v7
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}
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; CHECK-LABEL: mul_2
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; CHECK: r0 = memb(r0+#0)
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; CHECK: r1:0 = mpy(r2,r0)
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; CHECK: jumpr r31
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define i64 @mul_2(i8* %a0, i64 %a1) #0 {
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b2:
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%v3 = load i8, i8* %a0
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%v4 = sext i8 %v3 to i64
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%v5 = shl i64 %a1, 32
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%v6 = ashr exact i64 %v5, 32
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%v7 = mul nsw i64 %v6, %v4
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ret i64 %v7
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}
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; CHECK-LABEL: mul_acc_1
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; CHECK: r5:4 += mpy(r2,r0)
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; CHECK: r1:0 = combine(r5,r4)
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; CHECK: jumpr r31
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define i64 @mul_acc_1(i64 %a0, i64 %a1, i64 %a2) #0 {
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b3:
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%v4 = shl i64 %a0, 32
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%v5 = ashr exact i64 %v4, 32
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%v6 = shl i64 %a1, 32
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%v7 = ashr exact i64 %v6, 32
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%v8 = mul nsw i64 %v7, %v5
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%v9 = add i64 %a2, %v8
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ret i64 %v9
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}
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; CHECK-LABEL: mul_acc_2
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; CHECK: r2 = memw(r2+#0)
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; CHECK: r5:4 += mpy(r2,r0)
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; CHECK: r1:0 = combine(r5,r4)
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; CHECK: jumpr r31
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define i64 @mul_acc_2(i64 %a0, i32* %a1, i64 %a2) #0 {
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b3:
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%v4 = shl i64 %a0, 32
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%v5 = ashr exact i64 %v4, 32
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%v6 = load i32, i32* %a1
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%v7 = sext i32 %v6 to i64
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%v8 = mul nsw i64 %v7, %v5
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%v9 = add i64 %a2, %v8
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ret i64 %v9
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}
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; CHECK-LABEL: mul_nac_1
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; CHECK: r5:4 -= mpy(r2,r0)
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; CHECK: r1:0 = combine(r5,r4)
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; CHECK: jumpr r31
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define i64 @mul_nac_1(i64 %a0, i64 %a1, i64 %a2) #0 {
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b3:
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%v4 = shl i64 %a0, 32
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%v5 = ashr exact i64 %v4, 32
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%v6 = shl i64 %a1, 32
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%v7 = ashr exact i64 %v6, 32
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%v8 = mul nsw i64 %v7, %v5
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%v9 = sub i64 %a2, %v8
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ret i64 %v9
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}
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; CHECK-LABEL: mul_nac_2
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; CHECK: r1:0 = combine(r5,r4)
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; CHECK: r6 = memw(r0+#0)
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; CHECK: r1:0 -= mpy(r2,r6)
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; CHECK: jumpr r31
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define i64 @mul_nac_2(i32* %a0, i64 %a1, i64 %a2) #0 {
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b3:
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%v4 = load i32, i32* %a0
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%v5 = sext i32 %v4 to i64
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%v6 = shl i64 %a1, 32
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%v7 = ashr exact i64 %v6, 32
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%v8 = mul nsw i64 %v7, %v5
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%v9 = sub i64 %a2, %v8
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ret i64 %v9
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}
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attributes #0 = { nounwind }
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