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b82f729eb5
These instructions aren't universally available, but depend on a specific extension to the normal ARM architecture (rather than, say, v6/v7/...) so a new feature is appropriate. This also enables the feature by default on A-class cores which usually have these extensions, to avoid breaking existing code and act as a sensible default. llvm-svn: 179171
17 lines
534 B
Plaintext
17 lines
534 B
Plaintext
# RUN: llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 -disassemble -mattr=-trustzone < %s | FileCheck %s -check-prefix=NOTZ
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# RUN: llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 -disassemble -mattr=trustzone < %s | FileCheck %s -check-prefix=TZ
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#------------------------------------------------------------------------------
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# SMC
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#------------------------------------------------------------------------------
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0x7f 0x00 0x60 0xe1
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0x70 0x00 0x60 0x01
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# NOTZ-NOT: smc #15
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# NOTZ-NOT: smceq #0
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# TZ: smc #15
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# TZ: smceq #0
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