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24794481f6
If getHexUint reads in a hex 0, it will create an APInt with a value of 0. The number of active bits on this APInt is used to calculate the bitwidth of Result. The number of active bits is defined as an APInt's bitwidth - its number of leading 0s. Since this APInt is 0, its bitwidth and number of leading 0s are equal. Thus, Result is constructed with a bitwidth of 0, triggering an APInt assert. This commit fixes that by checking if the APInt is equal to 0, and setting the bitwidth to 32 if it is. Otherwise, it sets the bitwidth using getActiveBits. This caused issues when compiling MIR files with successor probabilities. In the case that a successor is tagged with a probability of 0, this assert would fire on debug builds. https://reviews.llvm.org/D37401 llvm-svn: 312387
40 lines
790 B
YAML
40 lines
790 B
YAML
# RUN: llc -o /dev/null %s
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# REQUIRES: asserts
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# Makes sure that having a probability of 0x00000000 to branch to a successor
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# doesn't hit an APInt assert in the MIParser.
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--- |
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define i32 @main() local_unnamed_addr #0 {
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entry:
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ret i32 0
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other:
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ret i32 0
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}
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attributes #0 = { nounwind }
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!llvm.module.flags = !{!0, !1}
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!llvm.ident = !{!2}
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!0 = !{i32 1, !"wchar_size", i32 4}
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!1 = !{i32 7, !"PIC Level", i32 2}
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!2 = !{!"clang version 6.0.0"}
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!3 = !{!"branch_weights", i32 0, i32 -1}
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...
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---
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name: main
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alignment: 2
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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successors: %bb.1.other(0x00000000)
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bb.1.other:
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...
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