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8bf97ed2ca
branches Looping over all terminators exposed AArch64 tests hitting an assert from analyzeBranch failing. I believe these cases were miscompiled before. e.g. fcmp s0, s1 b.ne LBB0_1 b.vc LBB0_2 b LBB0_2 LBB0_1: ; Large block LBB0_2: ; ... Both of the individual conditional branches need to be expanded, since neither can reach the final block. Split the original block into ones which analyzeBranch will be able to understand. llvm-svn: 279499
84 lines
2.0 KiB
LLVM
84 lines
2.0 KiB
LLVM
; RUN: llc -mtriple=aarch64-apple-darwin -aarch64-bcc-offset-bits=3 < %s | FileCheck %s
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; CHECK-LABEL: invert_bcc:
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: b.eq [[JUMP_BB1:LBB[0-9]+_[0-9]+]]
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; CHECK-NEXT: b [[JUMP_BB2:LBB[0-9]+_[0-9]+]]
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; CHECK-NEXT: [[JUMP_BB1]]:
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; CHECK-NEXT: b [[BB1:LBB[0-9]+_[0-9]+]]
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; CHECK-NEXT: [[JUMP_BB2]]:
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; CHECK-NEXT: b.vc [[BB2:LBB[0-9]+_[0-9]+]]
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; CHECK-NEXT: b [[BB1]]
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; CHECK: [[BB2]]: ; %bb2
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; CHECK: mov w{{[0-9]+}}, #9
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; CHECK: ret
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; CHECK: [[BB1]]: ; %bb1
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; CHECK: mov w{{[0-9]+}}, #42
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; CHECK: ret
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define i32 @invert_bcc(float %x, float %y) #0 {
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%1 = fcmp ueq float %x, %y
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br i1 %1, label %bb1, label %bb2
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bb2:
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call void asm sideeffect
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"nop
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nop",
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""() #0
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store volatile i32 9, i32* undef
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ret i32 1
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bb1:
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store volatile i32 42, i32* undef
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ret i32 0
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}
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declare i32 @foo() #0
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; CHECK-LABEL: _block_split:
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; CHECK: cmp w0, #5
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; CHECK-NEXT: b.eq [[LONG_BR_BB:LBB[0-9]+_[0-9]+]]
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; CHECK-NEXT: b [[LOR_LHS_FALSE_BB:LBB[0-9]+_[0-9]+]]
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; CHECK: [[LONG_BR_BB]]:
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; CHECK-NEXT: b [[IF_THEN_BB:LBB[0-9]+_[0-9]+]]
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; CHECK: [[LOR_LHS_FALSE_BB]]:
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; CHECK: cmp w{{[0-9]+}}, #16
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; CHECK-NEXT: b.le [[IF_THEN_BB]]
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; CHECK-NEXT: b [[IF_END_BB:LBB[0-9]+_[0-9]+]]
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; CHECK: [[IF_THEN_BB]]:
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; CHECK: bl _foo
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; CHECK-NOT: b L
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; CHECK: [[IF_END_BB]]:
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; CHECK: #0x7
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; CHECK: ret
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define i32 @block_split(i32 %a, i32 %b) #0 {
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entry:
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%cmp = icmp eq i32 %a, 5
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br i1 %cmp, label %if.then, label %lor.lhs.false
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lor.lhs.false: ; preds = %entry
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%cmp1 = icmp slt i32 %b, 7
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%mul = shl nsw i32 %b, 1
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%add = add nsw i32 %b, 1
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%cond = select i1 %cmp1, i32 %mul, i32 %add
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%cmp2 = icmp slt i32 %cond, 17
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br i1 %cmp2, label %if.then, label %if.end
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if.then: ; preds = %lor.lhs.false, %entry
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%call = tail call i32 @foo()
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br label %if.end
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if.end: ; preds = %if.then, %lor.lhs.false
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ret i32 7
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}
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attributes #0 = { nounwind }
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